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UNIVERSITY OF CALIFORNIA
Los Angeles
Device Design for Sub-0.1µm MOSFETs
for Sample and Hold Circuits
A thesis submitted in partial satisfaction
of the requirements for the degree Master of Science
in Electrical Engineering
by
Mayank Kumar Gupta
2003
Contents
1. Introduction...............................................................................................................1
1.1
Overview............................................................................................................1
1.2
Organization.......................................................................................................4
2. Modeling of the Gate Tunneling Current...............................................................6
2.1
Introduction........................................................................................................6
2.2
Tunneling through Silicon Dioxide ...................................................................7
2.2.1
Fowler-Nordheim Gate Tunneling .................................................... 7
2.2.2
Direct Tunneling ................................................................................8
2.2.2.1
Theory of Direct Tunneling...............................................11
2.3
Simulation Setup..............................................................................................12
2.4
Summary ..........................................................................................................16
3. Impact of Gate Tunneling on Sample and Hold Circuits....................................17
3.1
Introduction......................................................................................................17
3.2
Initial Setup and the Analysis ..........................................................................18
3.2.1
Initial Setup ......................................................................................18
3.2.2
Analysis............................................................................................21
iii
3.3
3.4
3.5
Performance Metrics........................................................................................25
3.3.1
Acquisition Time .................................................................................25
3.3.2
Nonlinearity .........................................................................................25
3.3.3
Pedestal Error.......................................................................................26
3.3.4
Droop Rate ...........................................................................................26
Sample and Hold Circuit Trade Offs ...............................................................27
3.4.1
Effect of Gate Oxide Thickness .......................................................28
3.4.2
Effect of Junction Depth ..................................................................32
3.4.3
Effect of Source Drain Extension Length ........................................35
3.4.4
Gate Length Scaling .........................................................................41
Summary..........................................................................................................43
4. Modeling of the Charge Injection in Sample and Hold Circuits ........................44
4.1
Introduction......................................................................................................44
4.2
Analytical Model .............................................................................................45
4.3
Results obtained from the Model.....................................................................57
4.3.1
Simulation Setup..................................................................................57
4.3.2
Variation of Components with Source Drain Extension Length..........59
4.3.3
Variation of Component with Gate Oxide Thickness ..........................63
4.3.4
Variation in components with Clock Droop Rate ................................64
4.4 Summary..........................................................................................................66
iv
5. Conclusion ...............................................................................................................67
6.
5.1
Summary ..........................................................................................................67
5.2
Future Work .....................................................................................................69
Bibliography ....................................................................................................... 71
v
List of Figures
1.1
Acceptable droop rates as a function of the A-D converter bit precision and the
Sampling frequency. The supply voltage is assumed to be 1volts...................................... 3
2.1
Band diagram showing the dominant mechanism via which the electrons can tun-
nel through the gate insulator. For sub 5nm oxide thickness, the direct tunneling current
component dominates the total gate leakage [14]. ............................................................. 7
2.2
Band diagram showing the various mechanisms via which the electrons (a), (b)
and the holes (c) can tunnel through the gate insulator material. For the tunneling process
(a), CBET, wave functions ψS1, ψS2 of the initial (right-hand) state and the final (lefthand) state of an elastic tunneling transition process are shown here. k1 and k2 (k2 › k1) are
the real wave numbers outside of the barrier region and κ(x) is the imaginary wave number inside the barrier region (0‹x‹tox).. .............................................................................. 9
2.3
Band diagram for the semiconductor oxide gate interface at various gate biases.
Note how the direction of the gate tunneling current in positive (into the gate) for the cases
(a), (b) and (c), and is negative (out of the gate) for the case (d). The gate tunneling current
in (a) and (c) flows via the channel and that in (b) and (d) is the Edge Direct Tunneling
(EDT), flowing in the gate-source/drain overlap region................................................... 10
2.4
Gate tunneling current for various oxide thicknesses. There is a good match
between the experimental [20] and the simulation data. ................................................. 13
vi
2.5(a) Simulated Ig-Vg and Id-Vg characteristics for PMOSFET with different oxide
thicknesses. The Vt of the devices was -0.25V ................................................................ 14
2.5(b) Simulated Ig-Vg and Id-Vg characteristics for NMOSFET with different oxide
thicknesses. The Vt of the devices was 0.25V.................................................................. 14
2.6
A comparison of the gate and drain currents as function of gate voltage. Note how
the gate leakage actually exceeds the Idrain for Vg‹0 V. The Tox for this device is 8Å.. 16
3.1
A basic sample and hold circuit, the NFET and the PFET are MEDICI devices,
whose parameters are varied. The load capacitances and the power supplies are assumed
to be ideal.......................................................................................................................... 18
3.2
Device structure considered in this study. Effects of Tox, SDE length, and Xj on
the performance of a S-H circuit are studied in this work. ............................................... 19
3.3
Input and output voltages of the sample and hold circuit. The sample and the hold
clock cycles are indicates by (S) and (H) respectively. .................................................... 21
3.4a
Electrodes current for NFET with Gate Tunneling Model turned off. The time
instances for sample and hold are indicated by arrows (S) and (H). Tox=10nm.............. 22
3.4b
Electrodes current for NFET with Gate Tunneling Model turned on. The time
instances for sample and hold are indicated by arrows (S) and (H). Tox=10nm.............. 22
3.5
Various capacitances between the junction and electrodes for a FET. The numerical
values are given in the Table 3.1....................................................................................... 23
3.6
Acquisition time as a function of the gate oxide thickness, all the devices had a Vt
of |0.25V| and hence the bulk doping varied for the devices............................................ 28
vii
3.7
Hold voltage droop rate as a function of the gate oxide thickness, all the devices
had a Vt of |0.25V| and hence the bulk doping varied for the devices ............................. 29
3.8
Integral nonlinearity as a function of the gate oxide thickness, all the devices had a
Vt of |0.25V| and hence the bulk doping varied for the devices. The two time instances
correspond to immediately after and 7.5ns after the clock falls to zero. The second curve
(red triangle) shows enhanced effect of the gate tunneling current. The inset shows the ∆V
due to charge injection as a function of the Tox. The curves relating to crest and trough correspond to the maximum and minimum source voltage respectively. The charge injection
is severe for the low source voltage case (trough) than for the high source voltage (crest)
[36].
............................................................................................................................... 30
3.9
Acquisition time as a function of the source drain junction depth, all the devices
have a Tox of 10Å and a Vt =|0.25V|................................................................................32
3.10
Equivalent circuit, with parasitic source-drain resistance. The pass gate is turned
“On”, with both NFET and PFET conducting ...................................................................32
3.11
Hold voltage droop rate as a function of the source drain junction depth, all the
devices had a Vt =|0.25V| and a Tox of 10Å .....................................................................33
3.12
∆V due to charge injection as a function of the Xj, all the devices have a Vt of
|0.25V|. The curves relating to crest and trough correspond to the maximum and minimum
source voltage respectively. Note how the charge injection is severe for the low source
voltage case (trough) than for the high source voltage (crest) [36]. ..................................34
3.13
Dimensions of the various junctions and the source drain extension length. Note
that all the profiles are uniform box profiles .....................................................................36
viii
3.14
Acquisition time as a function of the SDE length, all the devices have a Vt of
|0.25V| and similar Tox and Xj of 10Å and 13nm respectively. ........................................36
3.15
Hold Voltage droop rate as a function of the SDE length, all the devices have a Vt
of |0.25V| and similar Tox and Xj of 10Å and 13nm respectively.....................................37
3.16
On current of the pass gate, for NFET and PFET. Bias voltages are Vs=Vb=0 and
Vg=Vd=1.0Volts, all the devices have a Vt of |0.25V| and similar Tox and Xj of 10Å and
13nm respectively. .............................................................................................................38
3.17
Gate current of the NFET. Bias voltages are Vs=Vb=Vg=0 and Vd=1.0Volts, all
the devices have a Vt of |0.25V| and similar Tox of 10Å and Xj=13nm. The PFET gate
tunneling current was an order of magnitude smaller than that in the NFET....................38
3.18
Integral nonlinearity as a function of the source drain extension length, all the
devices had a Vt =|0.25V| with similar Tox=10Å and Xj=13nm. The two time instances
correspond to immediately after and 7.5ns after the clock falls to zero. The second curve
(red triangle) shows enhanced effect of the gate tunneling current. The inset shows ∆V due
to charge injection as a function of the SDE. The curves relating to crest and trough correspond to the maximum and minimum source voltage respectively. The charge injection is
severe for the low source voltage case (trough) than for the high source voltage (crest)
[36]
................................................................................................................................39
3.19
Acquisition time vs the gate length for devices with scaled Tox and a fixed Tox of
15Å. Vdd and Vth were kept fixed at 1.0V and |0.25V| respectively. .............................. 41
3.20
INL vs the gate length for devices with scaled Tox and a fixed Tox of 15Å. Vdd
and Vth were kept fixed at 1.0V and |0.25V| respectively................................................ 41
ix
4.1
Variation of the various components of the gate current with the applied gate bias,
hold mode starts at Vg≈0.73V, and the drain and source component of the gate current
become equal for the rest of the falling edge.................................................................... 50
4.2
Various components of the gate tunneling currents. Igso and Igdo are the parasitic
tunneling currents through gate source/drain overlap region. Igc is the gate-channel tunneling current, which is partitioned into Igcs and Igcd, flowing into the source and drain
respectively ....................................................................................................................... 51
4.3
Schematic representation of the band diagram for the case of a negative bias
applied at the n+ poly gate.................................................................................................53
4.4
Device structure and circuit topology considered for the model. ..........................58
4.5
Charge Injection Voltage due to the three major components of charge injection as
predicted by the model (solid line) and as obtained by detailed simulations (solid squares)
for various OL lengths. The source voltage is 0.73 volts and the droop rate is 2x108V/sec.
Capacitance values were taken from the Table 4.1........................................................... 61
4.6
Charge injection voltage due to the three major components of charge injection as
predicted by the model (solid line) and as obtained by detailed simulations (solid squares)
for various oxide thicknesses. The OL length and junction depth are kept fixed............. 63
4.7
Charge injection voltage due to the three major components of charge injection as
predicted by the model (solid line) and as obtained by detailed simulations (solid squares)
for various clock droop rates. The gate oxide thickness and the OL length are kept fixed.
Average source voltage is the same for all the devices......................................................65
x
List of Tables
3.1
Overlap capacitance for NFET Vs=Vs=0.73V Vg=Vsub=0V ..............................24
4.1
Overlap capacitance for different OL lengths........................................................60
xi
Acknowledgments
My stay at UCLA is dotted with people who have contributed either directly or
indirectly to the completion of this thesis work, much of which would not have been possible without their help and support. To start with, I would like to thank my parents and
sister for their continued patience, love and confidence in me. Every telephone call back
home renewed my hopes here.
I would like to thank my advisor, Professor Jason Woo, for his guidance, encouragement, support and confidence in me through the course of my studies at UCLA. Without his motivating discussions and unwavering desire for achieving high research
standards, this work would not have been possible. I am especially grateful to him for giving me the opportunity to work on such an exciting project and the freedom to pursue my
research interest. I wish to express my sincere gratitude towards Professors C.R.
Viswanathan and C.K. Ken Yang for their time to review this manuscript.
My sincere thanks to Girish for all the technical discussions, his invaluable suggestions and the white board sessions we had, which contributed considerably to my understanding of the subject matter. Not to forget the amount he spent proof reading my thesis.
Special thanks also goes to Sushant and Mayank Garg for the valuable technical discussions and all the fun we had throughout the course of this work. Sushant has been an elder
xii
brother through out my stay and for certain, I can never repay him back for all he has done
for me.
I would like to acknowledge my friends and colleagues Jun Yuan (the strongest
man around), Jae Kwan Park (grand dad), Alan Hsiung, Young Woo Park, Seong D. Kim,
Yun Xu and Yu-Lin Chao for maintaining a happy and encouraging work environment in
the lab. Special thanks to the two new students in the lab, Ritesh and Gaurav, for proofreading this manuscript. I wish them all great success in their future endeavors. Thanks to
Jun for giving me the occasional late night rides, the cookies and the chinese jokes.
I would also like to thank my friends Hemant (despo), Subal, Anshuman, Jatin,
Maneesh, Shalabh and Sachin Adlakha for all the fun I had at UCLA. Thanks to Juthika,
for the wonderful rides on the PCH and to my dear friends Deepak and Gaurav Bansal, for
being more concerned about my thesis than myself at times. It would be unfair if I did not
mention Prof Ramgopal Rao’s name, for he believed in me and I hope that I have done justice to his faith.
Last but certainly not the least, I would like to specially thank Louise Watson for
her moral support, affection and for taking care of all the chaos that I created when I came
to UCLA and all the nice words she had, when I graduated. Thanks to Leticia Dominguez,
Martha and Ilhee Choi for their help.
xiii
ABSTRACT OF THE THESIS
Device Design for Sub-0.1µm MOSFETs
for Sample and Hold Circuits
by
Mayank Kumar Gupta
Master of Science in Electrical Engineering
University of California, Los Angeles, 2003
Professor Jason C. S. Woo, Chair
Recent explosion in the demand for the mobile telecommunication, computing and
multimedia applications has driven the efforts to integrate analog blocks with the internal
logic core on a single chip. It is highly desirable that the traditional analog functional
blocks migrate easily to the digital CMOS processes. Sampling circuits, an essential part
of the ADCs, act as an interface between the analog world and the signal processing systems and hence must match the performance and speed of the overall system. Scaling of
the channel length, gate oxide thickness and the operational voltage, have brought about
many challenging device design issues for these circuits. Issues like droop rate of the sampled voltage and nonlinearity of the pass gate can be alleviated by using proper device
design. We have extensively studied how different device parameters affect these constituents of sampling circuit performance metric. It is shown that as the device is scaled into
sub-65nm regime for ADCs using moderate sampling rate and high resolutions, the gate
xiv
tunneling current will not only severely degrade the droop rate but also affect the nonlinearity adversely. The effect of scaling on various trade-offs that exist among metric constituents is also presented. Though many of the design requirements are defined by circuit
specifications, these device guidelines can be used to improve the sample and hold operation to a fairly general degree. We also present an analytical model for the gate induced
charge injection and other components of charge injection, which can be used to predict
the worst case injection for a given bias condition and tailor individual components.
xv
Chapter 1
Introduction
1.1 Overview
The continued downscaling of transistor dimensions in submicron CMOS technology is
driven by the need for increased speed and integration density in the state-of-the-art digital
IC systems. As the supply voltages are scaled proportional to the transistor dimensions,
the power dissipation of digital circuits is also reduced. While this trend is desirable for
digital systems, it makes the design of analog circuits very challenging [1]. Because analog circuits are routinely integrated with digital blocks today (e.g., data converters, filters,
etc.), it is highly desirable that traditional analog functions migrate easily to digital CMOS
processes. For logic applications where the Ion/Ioff trade-off dominates, the challenge is in
the reduction of the off-current without degrading the drive currents of the MOSFET. The
2-D penetration of the drain electric field through electro-static coupling, increases the
thermal diffusion current due to drain induced barrier lowering (DIBL). Several other
mechanisms such as drain-to-gate leakage, drain-to-body junction leakage and ultimately
1
the drain-to-source tunneling limits the Ioff [2-3]. Whereas, the channel mobility, average
carrier drift velocity, the channel charge density and source drain resistance (RS/D) decide
the Ion. Several novel structures such as super steep retrograde (SSR), super halo, elevated
source drain structures are being used for deep sub-micron devices for bulk CMOS technology to improve the Ion/Ioff trade-off [4]. However, it has been observed that the devices
optimized for higher digital performance, have poor analog performance and vice-versa
[5]. This brings renewed attention to the difficult analog IC design challenges ahead. One
of the key limitations of future CMOS technologies remains the restricted supply voltage,
limited primarily by the thin gate oxide that is prone to voltage stress (reliability) and
excessive leakage [6]. One class of circuits strongly affected by this trend is switchedcapacitor (SC) circuits, that are used in many analog signal processing applications including a majority of CMOS data converters. The minimum “On” resistance of the CMOS
pass gate, an essential component of any switched capacitor circuit, is limited by maximum overdrive voltage for a given Vdd, which reduces with the scaling of the gate length.
There are several well-known solutions to bypass this problem. These approaches include:
1) the clock boosting schemes (e.g. clock signal) which cannot be used in submicron lowvoltage CMOS processes as the gate oxide can only tolerate the technology’s maximum
voltage [8]; 2) the use of scaled/lower threshold transistors, which are not always scalable
to very low voltage supplies as they could suffer from an unacceptable amount of leakage
current (i.e., the switch may not fully turn off) [9].
Scaling of the MOSFET gate length demands that the device is designed such that
it still meets the circuit figure of merits, while keeping the device related concerns to the
2
minimum. As mentioned earlier, the scaling of the gate oxide thickness with channel
length also limits the maximum voltage that a MOSFET gate oxide can tolerate, before the
gate leakage becomes unacceptable. This leakage current not only affects the magnitude
of the voltage on the storage capacitor, but also the linearity of the sampled voltage. For
A-D converters, the leakage current also sets a limit to the maximum acceptable droop rate
the given sample and hold pass gate can tolerate. If the number of bit in a A-D converter
are increased for greater accuracy, the margin for error due to INL and charge leakage
reduces very rapidly. Also if the sampling frequency of the A-D converter is small, it is
more likely that the charge on the sampling capacitor will leak out of the storage capacitor
in the long hold time. Fig 1.1 shows the acceptable droop rate for a given sampling frequency and A-D conversion precision, for a 1Volt supply voltage. Here we have
Figure 1.1: Acceptable droop rates as a function of the A-D converter bit
precision and the sampling frequency. The supply voltage is assumed to
be 1volts and the leakage from the following stages is not considered.
3
negelected the effect of leakage from the following stages. It is seen that for current state
of the art ADC with precision of 10-12 bits and operating frequency of 30-50Mhz [10],
the acceptable limit of the droop rate is 104V/sec. This constrain is relaxed for ADCs that
compromise extremely high sampling frequencies with the precision of analog to digital
conversion [11]. The scaling of the voltage supply also gives rise to reduced dynamic
range of the ADCs and degraded signal to noise and distortion ratios (SNDR). All these
issues necessitate a comprehensive study, on the merits and demerits of scaling the channel length for analog application in switched capacitors circuits.
1.2 Organization
This thesis is organized into five chapters. In chapter 2 various gate tunneling
mechanisms and the issues related to gate direct tunneling are discussed. In order to gain
insight into the circuit behavior of scaled MOSFETs in sample and hold circuits, details of
the model used by the device simulator MEDICI are given. Paths via which the gate tunneling current flow are explained using detailed band diagrams and the reasons behind
their relative magnitudes elaborated. We also talk about the calibration of the simulation
model to match the experimental data.
In order to observe the various trade-offs that exist among the constituents of sample and hold circuit performance metrics and their dependence on device design, several
simulations were carried out. In Chapter 3, the impact of device parameters like oxide
thickness, bulk doping, source drain extension length and junction depth on the performance of 50nm MOSFET in a sample and hold circuit have been discussed. We also dis-
4
cuss the reasons behind the observed behavior and how our understanding of the device
physics can help us better design sample and hold circuits.
With scaling of the gate oxide thickness the gate leakage current of the MOSFETs
increases to the order of a few tens of Amps/cm2. With such high leakage current, exact
modeling of the gate induced charge injection in very important. Since the charge injection also affects the nonlinearity of the overall circuit, significance of such a modeling is
double folds. Detailed analytic models with accurate incorporation of device parameters
and circuit bias have been formulated. Based on these formulae, the impact of varying different device parameters on the performance of the sample and hold circuit have also been
discussed.
Finally, in chapter 5, a summary of the conclusions of this work are presented.
Some suggestions regarding the future work that can be pursued are also discussed.
5
Chapter 2
Modeling of the Gate Tunneling
Current
2.1 Introduction
Aggressive scaling of metal-oxide-semiconductor (MOS) devices has resulted in the use
of ultra thin gate oxides, which, in turn, enhanced device performance. According to the
International Technological Roadmap for Semiconductors (ITRS), effective oxide thickness (EOT) of 1.2-1.5nm will be required by 2004 for sub-100nm CMOS. Current
research works have identified several physical limiting factors associated with the ultra
thin gate oxides, including direct tunneling currents and oxide reliability. Among them,
the tunneling current is the one most sensitive to the oxide thickness. As the thickness of
the oxide layer decreases, the tunneling current increases exponentialy. This increased
current, not only adversely affects the MOS device performance but also significantly
increases the standby power consumption of a highly integrated circuit [12]. In this chapter the focus is on the model that is used by MEDICI for simulation of the gate tunneling
6
current and its calibration to match the simulated device characteristics with that of experimental devices.
2.2 Tunneling through Silicon Dioxide
When a large positive bias is applied to the gate electrode, electrons in the strongly
inverted surface can tunnel into or through the oxide layer and hence give rise to a gate
current, Figure 2.1. Similarly if a large negative bias is applied to a heavily doped n+ poly
gate, electrons from the n+ poly Si can tunnel into or through the oxide layer. Since we are
focusing on sub 100nm devices, we will discuss two of the major mechanism for gate tunneling current.
2.2.1 Fowler-Nordheim Gate Tunneling:
This type of tunneling occurs when the electrons tunnel into the conduction band of the
oxide layer. Figure 2.1 illustrates the Fowler-Nordheim tunneling of electrons from the
Thermionic Emission
Fowler-Nordheim
Direct Tunneling
Figure 2.1: Band diagram showing the dominant mechanism via which the electrons can tunnel through the gate insulator. For sub 5nm oxide thickness, the
direct tunneling current component dominates the total gate leakage [14].
7
silicon surface inversion layer into the conduction band of the oxide via a triangular barrier. For the simplest case the Fowler-Nordhein current can be modeled by the equation
[13]:
3⁄2
q ⋅ E ox
 8π 2m∗ φ ox

J FN = ---------------------- ⋅ exp  – --------------------------------------- 
8πhφ ox
3hqE ox


3
2
Eq 2.1
This is obtained by applying the WKB approximation for a triangular barrier. Here Eox is
the electric field in the oxide, φox denotes the Si-SiO2 interface energy barrier for electrons and m* is the effective mass of the tunneling electron. At an oxide field of 8MV/cm,
the measured Fowler-Nordhein tunneling current density is about 5x10-7A/cm2 [14]. As
we shall see in the next section such magnitudes are very small when compared to the
direct tunneling component of gate tunneling.
2.2.2 Direct Tunneling.
Figure 2.2 shows the various components of the gate direct tunneling current for a positively biased n-channel MOSFET, with the n+ poly Si gate. Direct tunneling of electrons
in the (a) conduction band, (lets call this component CBET) (b) valence band, (call this
VBET), of the p-substrate into the n+ poly gate is illustrated. Also the tunneling of (c) the
holes from the valence band in the n+ poly gate into the p-substrate (call this VBHT) is
shown. The direct tunneling current can be modeled as given in Eq 2.2 [15]. The tunneling barrier height of 3.1eV for CBET, 4.2eV for VBET and 4.5eV for VBHT, largely
determines the contribution due to each mechanism. The component (a), CBET, with the
lowest barrier height is the predominant of the three leakage mechanisms.
8
3⁄2
– B ( 1 – ( 1 – V ox ⁄ φ ox ) )
------------------------------------------------------------V ox ⁄ t ox
2
Eq 2.2
J DT = C ( V ox ⁄ t ox ) e
Here B and C are physical parameters [15] that take into account the voltage dependence
of the densities of states at the electrode interface and the effective masses in the oxide
[16]. In the equation, tox is the oxide thickness and Vox is the oxide voltage, which can be
related to the applied gate bias (Vgs) and the surface potential (ϕs) as follows:
Eq 2.3
V ox = V gs – V fb – ϕ s
tox
Electron
φox 3.1eV
Hole
(a) CBET
Ec
Ef
4.2eV
Ec
Ef
Ev
(b) VBET
SiO2
(c) VBHT
Ev
4.5eV
n+ poly gate
p substrate
qVOX
k2 ΨS2
k1 ΨS1
κ
Figure 2.2: Band diagram showing the various mechanisms via which the electrons (a), (b) and the holes (c) can tunnel through the gate insulator material. For
the tunneling process (a), CBET, wave function ψS1 of the initial (right-hand)
state and ψS2, the final (left-hand) state of an elastic tunneling transition process
are shown here. k1 and k2 (k2 › k1) are the real wave numbers outside of the barrier
region and κ(x) is the imaginary wave number inside the barrier region (0‹x‹tox).
9
Ec
Ec
Ec
Ef
Ef
EV
p Doped
Channel Region
Gate
Electrode
Ef
Ec
Ef
EV
n+ S/D Extension
Gate
Electrode
(b)
(a)
Vgate › 0
Ec
Ec
Ef
Ef
EV
Gate
Electrode
Ec
Ef
Ec
Gate
Electrode
Ef
p Doped
Channel Region
EV
+
n S/D Extension
(c)
(d)
Vgate ‹ 0
Figure 2.3: Band diagram for the semiconductor oxide gate interface at various gate
biases. Note how the direction of the gate tunneling current in positive (in to the gate)
for the cases (a), (b) and (c), and is negative (out of the gate) for the case (d). The
gate tunneling current in (a) and (c) flows via the channel and that in (b) and (d) is
the Edge Direct Tunneling (EDT), flowing in the gate-source/drain overlap region.
Figure 2.3, illustrates the band structures for various gate biases. We realize that
the dominant leakage mechanism, CBET, has different polarities for different cases; into
the gate electrode (positive) for the cases (a), (b) and (c) and out of the gate electrode
(negative) for the case (d). Also the magnitude of the CBET current varies in the different
regions of the MOSFET. The channel component of the gate current dominates the edge
10
direct tunneling (EDT) for certain biases (Vg › 0) and vice versa happens for other biases
(Vg ‹ 0).
2.2.2.1 Theory of Direct Tunneling
The model that was used by the device simulator, calculates direct tunneling from
three sources: conduction band electron tunneling (CBET), valence band electron tunneling (VBET), and valence band hole tunneling (VBHT).
The tunneling current is derived using Bardeen’s transition probability approach
[17] and Harrison’s independent-particle tunneling model [18]. Figure 2.2 shows a onedimensional energy band diagram of a trapezoidal SiO2 barrier sandwiched between two
silicon layers. The probability per unit time of transition for an electron in state ΨS1 to
ΨS2 (where ΨS1 and ΨS2 denote the quantum mechanical wave functions) is described by
Fermi’s golden rule: P12=(4π2/h)|M12|2ρ2 f1(1-f2). Where M12 is the matrix element to be
evaluated between ΨS1 and ΨS2 in the tunneling region. As shown by Bardeen [17],
M= -ihJ/2π, where J is the current density operator. ρ2 is the density of final states, and f1
and f2 are occupation probabilities of the initial and final states, respectively.
Following the approach given by Cai J. et.al. [19], for conduction band electron
tunneling, noting that the initial and final state differ by qVGB, where the VGB is the
applied gate-to-substrate voltage bias, we get the formulation of the net tunneling current
across the insulator as given in Eq 2.4.
4πqm k B Tr
1
DOS
J
= ---------------------------------------DT
3
h
Eb
( E Fn1 – E c1 – E ) ⁄ k B T
+1
e
TC ( E ) ln ---------------------------------------------------------------------------------------( E Fn1 – E c1 – E – V GB ) ⁄ k B T
e
+1
0
∫
11
dE
Eq 2.4
Where the integral is over the vertical kinetic energy, Eb, of the incident electrons.
With reference to Figure 2.2, EFn1, Ec1, and m1 are the electron quasi-fermi level, the conduction band edge, and the electron effective tunneling mass, respectively in the silicon
substrate at the insulator interface. The effective density of states mass, is given by
rDOS.m1, where rDOS is the density-of-states scaling factor which is typically on the order
of 1. The endpoint of the integration is determined by the barrier height, Eb1. The electron
charge is given by q, h is Planck’s constant, and kBT is the thermal energy. TC(E) is the
tunneling coefficient of an electron with energy E. The values of conduction, valence
band energies and electron quasi-fermi levels are replaced by relevant values for VBET
and VHBT [20].
2.3 Simulation Setup
For the purpose of this study we used the device simulator, Medici [21]. Medici enables
gate current analysis using a self-consistent model. After obtaining a solution, MEDICI
calculates the amount of current collected by the gate for each bias or time point from the
available physical quantities, such as electric field and current density, within the structure
.
During the evaluation of the gate current, the tool computes electron and hole gate
current at each point along all semiconductor-insulator interfaces. Electric field lines in
the insulator are followed to determine the final location for the injected electron and hole
current. In self-consistent mode, the direct tunneling current acts as a self-consistent
boundary condition for the electron and hole currents along semiconductor/insulator inter-
12
faces. Through out the study we have used the self-consistent model which insured that
the electron and hole continuity equations were solved at the insulator and semiconductor
interface.
In order to calibrate the model to the experimental data, we tuned several parameters of the direct tunneling model. Using the experimental data from [22], we modeled the
gate direct tunneling current through silicon oxide of varying thicknesses of 13Å, 15Å and
18Å. These are large gate devices so as to minimize the effect of process induced variations that would other wise corrupt the validity of the model. The device doping and other
parameters were kept the same. The Figure 2.4 shows the results for the 13Å, 15Å and
18Å for the Tox. As can be seen, by using the various parameters of the gate insulator
material, we were able to match the simulated data to the experimental values to a good
102
101
Gate Current (Amps/cm2)
100
10-1
10-2
10-3
Experimental Data 13Å
Tuned:Tox13Å
10-4
10-5
Experimental Data 15Å
Tuned:Tox15Å
Experimental Data 18Å
-6
10
10-7
Tuned:Tox18Å
-8
10
0.0
0.2
0.4
0.6
Gate Voltage (volts)
0.8
1.0
Figure 2.4: Gate tunneling current for various oxide thicknesses. There is a
good match between the experimental [22] and the simulation data.
13
extent. It should be noted that this is a simulation study and the values of the metrics
quantities can vary depending on the fabrication process, however, the trends are expected
to be the same as presented in this study.
The parameters of the gate insulator material that were tuned in the simulation
model were that of ME.DT, the effective tunneling mass of the electrons in the conduction
band of the oxide and MESC.DT, density of state mass scale factor for electron. The tuned
parameters were then used to simulate the gate direct tunneling current via oxide of various thicknesses. The same leakage parameters were used to simulate the leakage current
in the PMOSFET devices. It can be seen in Figure 2.5 that the gate leakage current in
PMOS devices is significantly less than that of the NMOS devices. This is due to the fact
that holes have a heavier mass than the electron and the tunneling barrier height (4.5eV)
Id-Vg Tox=10Å
Ig-Vg Tox=10Å
Id-Vg Tox=13Å
Ig-Vg Tox=13Å
Id-Vg Tox=15Å
Ig-Vg Tox=15Å
-1.0 -0.9 -0.8 -0.7 -0.6
10-4
10-5
10-6
10-7
10-8
10-9
10-10
10-11
10-12
10-13
10-14
10-15
-0.5 -0.4 -0.3 -0.2 -0.1 0.0
Electrode Current (Amps/µm)
that they have to overcome is much greater than that for a electron (3.1eV) [23]. Hence
10-4
10-5
10-6
10-7
10-8
10-9
10-10
10-11
10-12
10-13
10-14
0.0 0.1 0.2 0.3 0.4 0.5 0.6
0.7 0.8 0.9 1.0
Gate Voltage Vg (Volts)
Gate Voltage Vg (Volts)
Figure 2.5 (a): Simulated Ig-Vg and IdVg characteristics for PMOSFET with
different oxide thicknesses. The Vt of
the devices was -0.25V
Id-Vg Tox=10Å
Ig-Vg Tox=10Å
Id-Vg Tox=13Å
Ig-Vg Tox=13Å
Id-Vg Tox=15Å
Ig-Vg Tox=15Å
Figure 2.5 (b): Simulated Ig-Vg and IdVg characteristics for NMOSFET with
different oxide thicknesses. The Vt of
the devices was 0.25V
14
the probability that holes tunnel through the gate oxide is small when compared to that of
electrons. This is a significant step forward from the pessimistic approach in [22] where
the PMOS gate tunneling current was assumed to be as high as that of the NMOS for circuit performance evaluation. As we shall show in the chapter 4, the adverse effects of the
NFET gate tunneling current can not be compensated by the PFET gate current and this
leads to gate induced charge injection that cannot be compensated by usual circuit techniques. This is a critical issue when modeling the charge injection and droop rate due to
the gate tunneling current.
A point to note here is that by changing the set of model parameters for one of the
devices, we were able to match the leakage current for the other devices too, with the
same set of parameter values. This is very crucial to our approach since after calibrating
our model for these oxide thicknesses, we would like to vary the device parameters over a
wide range and still obtain meaning full and consistent results. Also, in Fig 2.5, we see
that if we compare the drain current and the gate direct tunneling current, for various
oxide thicknesses, it appears that the gate tunneling current is still a very small fraction of
the total “On” current. This is true only if we operate in a bias range such that Vgate ›
Vsource or Vdrain. Recent studies have shown that direct tunneling current appearing
between the source–drain extension (SDE) and the gate overlap, called the Edge Direct
Tunneling (EDT), dominates off-state drive current, especially in very short channel
devices [12], [16]. Shown in the Figure 2.6, the EDT current starts to dominate the total
MOSFET current in the off regime of the MOSFET. As the gate voltage is negative, the
source to drain current due to the channel charge is negligible (sub threshold region).
15
10-4
10-5
Current (Amp/µm)
10-6
I Drain
I Gate
10-7
10-8
10-9
10-10
10-11
10-12
-1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4
Gate Voltage (Volts)
0.6
0.8
1.0
Figure 2.6: A comparison of the gate and drain currents as
function of gate voltage. Note how the gate leakage actually
exceeds the Idrain for Vg‹0 V. The Tox for this device is 8Å
However as can be observed from Fig 2.3(d), the excessive tunneling of the electron from
the gate electrode to the S/D overlap region, causes the gate tunneling component to dominate. The fact that the gate leakage current can actually dominate the turn-off current of
the MOSFET is an issue for concern, because in sample and hold circuits, even a small
turn-off current is not acceptable.
2.4 Summary
In this chapter we elaborate on the gate tunneling model used in MEDICI and give
a physical explanation as to how the gate current can exceed the subthreshold current for
certain biases, for extremely thin gate dielectrics. Also the magnitudes of the gate tunneling current of PMOS and NMOS were compared.
16
Chapter 3
Impact of Gate Tunneling on Sample and Hold Circuits.
3.1 Introduction
Sampling Circuits act as an interface between the analog world and the signal processing
systems and hence must match the performance and speed of the overall system. These
circuits are an essential part of the ADCs and are used in the front end of A/D converters
to relax their timing requirements and at the back end of D/A converters to suppress their
glitch impulse [24]. A simple S-H circuit is designed by a sampling CMOS switch followed by a hold capacitor, as shown in the Fig 3.1. Unlike other analog circuits, like the
common source amplifier and other amplifier topologies, the gate leakage current has a
very important effect on the sample and hold circuit. This is due to the fact that when a
clock voltage of Vdd is applied at the gates of the FETs in the sample and hold circuit, the
gate currents can be very high. This is unlike the case of an amplifier circuit where the
FETs are biased near the threshold voltage, to minimize the overdrive voltage and to
17
Clock
PFET
Vin
Vout
Source
o
0.25Sinωt 0
0.5V
Drain
Load Capacitor
AC Source
DC Source
NFET
Clock
Figure 3.1: A basic sample and hold circuit, the NFET and the
PFET are MEDICI devices, whose parameters are varied. The
load capacitances and the power supplies are assumed to be ideal.
achieve a high value of gm. For gate lengths of sub 100nm as in this study, the gate oxide
thickness is of the order of a few nanometers. In such circumstances the gate leakage can
be as high as 100A/cm2 [25]. Such high values of gate current are of great concern, taking
into consideration the fact that they can easily affect the charge on the storage capacitor
and hence the final sampled voltage. Sample and hold circuits, as well as all circuits that
use the switched capacitor topology, are likely to be affected by these issues.
3.2 Initial Setup and the Analysis of the Sample and
Hold Circuit:
3.2.1 Initial Setup:
The basic structure used in the simulations is shown in Figure 3.2. Devices with a fixed
gate length of 50nm and oxide thickness, Tox, in the range of 0.8nm to 1.8nm were considered to probe the range around the 13Å thickness, as specified by ITRS for a 50nm gate
18
2λ
3λ
Vg
Gate
Vs
Deep S/D
Depth
Vd
Tox
Xj
Source
NS/D
Lg
LSDE
NA
Drain
NSDE
Figure 3.2: Device structure considered in this study. Effects of Tox, SDE
length, and Xj on the performance of a S-H circuit are studied in this work.
length. The source drain extension (SDE) depth, Xj, was varied around 13nm, (ITRS
specification for 50nm gate lengths [26]) from 8nm to 20nm. Variations in the SDE
length, LSDE, would lead to devices with varying short channel effects (SCE). The variation in SCE will be used to explain the characteristics of different devices in the later sections. According to ITRS, for gate length of 50nm, metal gate electrodes would be
introduced, but a sizable part of recent research is still based on poly gate electrodes [2730]. This is due to the fact that the choice of metal with a suitable workfunction is still an
active research field work and it will take some time before it is introduced as an industry
standard. Thus for the purpose of this study we have choosen doped poly Si as the gate
electrode material. Substrate doping is varied from 7.5x1017/cm3 to 1.5x1018/cm3, this
insured that for a n+ poly gate, the threshold voltage for the devices was roughly
0.25Volts. Similarly the bulk doping of the PMOS was so adjusted to achieve a Vt of 0.25V, with a p+ poly gate. SDE doping of 1.15x1019/cm3, deep source/drain depth of
30nm and doping of 1x1020/cm3 are kept constant for all NMOS and PMOS devices. Cur-
19
rent manufacturing techniques like laser annealing and pre-amorphization implants allow
fabrication of box like profiles [31]. Such devices offer good short channel and excellent
device characteristics [32]. For this reason we have assumed uniform doping profiles and
abrupt junctions for all the devices. The widths of the NMOS and the PMOS were 10µ m
and 20µ m respectively, this done in order to compensate for the mobility difference
between the electrons and the holes.
The clock voltage applied at the gate of MOSFETs has a peak value of 1V. The
voltage to be sampled, applied at the source of the MOSFET is a 0.5V peak to peak sinusoid in series with a 0.5V DC signal, Figure 3.2, this was in done in order to probe the onoff regimes of both the PMOS and the NMOS. With the input voltage variation of 0.250.75V, presence of PMOS and NMOS ensures that the on resistance remained nearly the
same for all these devices. It would have been interesting to apply a complete rail to rail
voltage swing, to the source of the pass gate, to evaluate the effect of nonlinearity; convergence issues constrained the use of this voltage range. The voltage supply at the input of
the pass gate and at clocks are ideal voltage sources, with zero input impedance. This
insured that the circuit related issues do not affect the device driven characteristics of the
pass gate. The load capacitor is 0.53pF, this is approximately 10times the total gate capacitance (Cox) of the NFET and PFET, for a Tox of 10Å and this value of capacitance was
kept fixed for all the simulated devices. For ADCs the kT/C noise in regards to the resolution of the ADC dictates the value of the load capacitor. So if we asssume that the resolution of the ADC is not changing across the devices, the fixed value of the storage
capacitor fairly justified. The frequency of the AC signal applied to the input of the pass is
20
1.1
Clock
Clock
Input Voltage
Output Voltage
Voltage (Volts)
0.9
0.7
0.5
0.3
0.1
-0.1
0.0
(S)
(S)
(H)
(S)
4.0x10-7
2.0x10-7
Time (sec.)
(H)
6.0x10-7
Figure 3.3: Input and output voltages of the sample and hold circuit. The
sample and the hold clock cycles are indicated by (S) and (H) respectively.
gate is 2Mhz. This was chosen sufficiently high to ensure that the overlap and junction
displacement currents also form an important part of the entire analysis, as it happens in
real circuits. Similar to actual circuit situation, the substrate of the NMOS and the PMOS
are connected to the GND and VDD respectively. The clock used for all the simulations
has a period of 300ns (3.33Mhz) and a realistic droop rate of 5ns. The duty cycle of the
clock was 50%.
3.2.2 Analysis:
Using the mixed mode simulations, we can obtain the node voltages and the currents into the nodes for various nodes as defined in the SPICE like circuit description.
Figure 3.3 shows the input sinusoid and output voltage vs. time for the sample and hold
circuit. The sample and hold instance are explicitly shows by (S) and (H). If we look
closely at Vout for the hold instances we see that it has a slope associated with it. This
21
slope is due to a leakage current flowing out of the sampling capacitor. There are three
leakage paths for the current to flow. One is via the subthreshold current flowing in the
channel of the FETs, and then there is a leakage current flowing due to junction leakage of
the reverse biased body-drain (p-n) junction and finally the gate leakage current, which
leaks away the charge on the capacitor. Of these three components the junction leakage is
very small in magnitude when compared to the other two components. Also at the instant
when the pass gate is switched off, there is charge injection from the channel and the
clock on to the sampling capacitor. This would be indicated by a slight increase in the
sampled voltage right at the beginning of the hold cycle (positive because the contribution
of the pMOSFET is greater due to is larger width). Charge injection for a S-H circuit has
10-2
10-2
Current (Amps)
10
Idrain
Isubstrate
Isource
Igate
10-6
-4
10
Current (Amps)
-4
(H)
10-8
10-10
10-12
0.00
2.25x10-7
(H)
10-8
10-12
7.5x10-8 1.5x10-7
Isource
Igate
10-6
10-10
(S)
Idrain
Isubstrate
0.00
3.0x10-7
(S)
7.5x10-8 1.5x10-7
2.25x10-7
3.0x10-7
Time(sec)
Time (sec)
Figure 3.4 (b): Electrodes current for
NFET with gate tunneling model turned
on. The time instance for sample and
hold are indicated by arrows (S) and (H).
Tox=10nm. Input voltage corresponds to
the initial clock cycle in Fig 3.3.
Figure 3.4 (a): Electrodes current for
NFET with gate tunneling model turned
off. The time instances for sample and
hold are indicated by arrows (S) and (H).
Tox=10nm. Input voltage corresponds to
the initial clock cycle in Fig 3.3.
22
been modeled in detail in Chapter 4 and quantified in section 3.3.3. The various currents
flowing into the electrodes of the NFET of the pass gate have been shown in Figure 3.4.
These currents correspond to the voltage waveform for one complete clock cycle as
shown in Figure 3.3. By turning off and on the gate tunneling current in simulations, we
are able to identify the effect of the gate current. The gate tunneling current is one of the
components that we are really concerned about, since the drain is connected to the sampling capacitor and any drain current that flows out of the gate, (as the gate current) during
the hold state would imply that voltage on the capacitor is disturbed. In Figure 3.4(a) with
the gate tunneling model off, the drain current is very small of the order of 10-11Amp for
the 10µ m NFET. The displacement current flowing out of the drain is very small since
the drain potential is almost fixed. All of the gate current flowing in this case is due to the
displacement current flowing via the overlap capacitance between the source electrode
(potential varying at 2Mhz) and the gate (potential fixed). Figure 3.5, details the various
0.00 Volts
0.73Volts
Cgate-source
Gate
Ctox
Source
Csource-body
0.73 Volts
Cgate-drain
Drain
Cbody
Cdrain-body
Substrate
0.00 Volts
Figure 3.5: Various Capacitance between the junction and electrodes for a FET. The numerical values are given in the Table 3.1.
23
capacitances that exist between the junctions and the electrodes of the NFET. The values
of these capacitances are tabulated in Table 3.1, and were obtained using RF analysis in
the ATLAS device simulator [33]. The corresponding bias voltages are shown in Figure
3.5, which corresponds to the first hold instant in the Figure 3.3, t=1.5x10-7secs. With the
source voltage decreasing at the falling edge of the clock there is displacement current
flowing into the source junction from the substrate and the gate. This also explains the relatively fixed Isubstrate for the hold cycle. In the Figure 3.4(b), the gate leakage current adds
to the drain current and now the drain current is three orders of magnitude higher (1008Amp
for the 10µ m NFET), than in Figure 3.4(a). This illustrates that with thinning of
the gate oxide, enhanced gate current can potentially affect the performance of a S-H circuit adversely
Electrodes
Capacitance
Cgate-source(fFarad/µm)
0.16
Cgate-drain(fFarad/µm)
0.15
Csource-body(fFarad/µm)
0.18
Cdrain-body(fFarad/µm)
0.17
Cox+ Cbody(fFarad/µm)
0.08
Table 1: Overlap capacitance for NFET Vs=Vs=0.73V Vg=Vsub=0V
24
3.3 Performance Metric:
In order to characterize sampling circuit thoroughly, a large number of performance metrics must be evaluated. In this work we have looked at some of the important metrics and
evaluated how the various device parameters affect them. These are [34]:
3.3.1 Acquisition Time:
Tacq is the time after the sampling command, required for the S-H amplifier output
to undergo a full scale transition and settle with in a specified error band around the final
value. This is determined by the “On” resistance of the CMOS switch, the value of the
hold capacitor, parasitic capacitances and the maximum allowed error in the final voltage.
For the purpose of this study we used a 0.01% error margin.
For this study, we apply a 1V dc at the input of the pass gate, with the storage
capacitor initially discharged and then turn on the pass gate. We measure the time it takes
for the voltage on the storage capacitor to reach 99.99% of its final value. The time taken
for the storage capacitor to completely discharge from Vdd, once the pass gate is turned
on, showed similar trends with device parameters variation.
3.3.2 Nonlinearity Error
There can be two kinds of nonlinearities (NL). Integral NL which is the maximum
deviation of the S-H output characteristics from a straight line for a linear increase in the
input. The difference between the ideal and the actual characteristics is called the INL
profile. The Differential NL is the maximum deviation in the output step from the ideal
value of one least significant bit, (LSB). Since in this study only the basic sampling was
25
analyzed and there was no conversion to bits, DNL could not be quantified, INL for the
various devices has been measured and plotted. The nonlinearity error originates from the
varying channel resistance for different values of the input voltages. The variation of the
threshold voltage with the source bias causes the FETs to have different overdrives for the
same gate voltage, thus different overdrives and the different channel “On” resistances.
For the quantification of this metric, a varying DC potential was applied to the
source of the pass gate and the output was allowed to settle (tsettling=12.5ns, with a full
swing Tacq of the order of 0.6ns). After this, the pass gate was switched off and the sampled voltage measured. Further details of INL measurement are given in section 3.4.1.
3.3.3 Pedestal Error:
The pedestal voltage is the error introduced at the S/H output during the transition
from sample to hold. This error stems from the channel charge injected by the CMOS
switch onto the storage capacitor when the switch turns off. Also adding to the voltage on
the storage capacitor is a component of the clock feed through which arises due to the gate
drain overlap capacitance. For sub 100nm devices, a part of gate tunneling current also
adds to the injected charge on the sampling capacitor. This gate induced charge injection
is studied in great detail in Chapter 4.
3.3.4 Droop Rate:
The droop rate is the rate of discharge of the leakage capacitor during the hold
mode. We measure the droop rate by evaluating how much the sampled voltage degrades
in the entire hold cycle, assuming the leakage current is constant (fixed droop rate slope).
Ideally the CMOS switch should not conduct any current in the off state and this rate
26
should be zero. In reality due to the subthreshold leakage of the FET and the junction
leakage of the body-drain junction, a small current conducts even when the applied gate
voltage is zero. This fact is further aggravated by the fact that as the CMOS switch is
scaled down and the gate oxide insulator thins and it starts conducting current due to gate
tunneling current. In the following sections we have quantified the effect of the devices
parameters on the droop rate. In the simulations, we measure the droop rate as the voltage
drop in the storage capacitor from the instant the pass gate turns off to the instant when it
next turns on.
3.4 Sample and Hold Circuits Trade off.
Device designers have control over several process parameters for a given technology node. For a fixed gate length, parameters like the gate oxide thickness, bulk doping, the junctions depth, source drain extension length (defined by the angle implant) can
be varied to an extent as per the design needs. Various trade-offs exist between the different performance criterions for the sample and hold circuit and these device parameters. In
this section we have tried to quantify the various trade-offs as different device parameters
are varied. We varied the aforementioned devices parameters to evaluate the effect of
these parameters on various metrics. Each point in the following graphs would correspond
to a different device with one of the parameters varied. Taking the SIA roadmap in to consideration, a device with 50nm gate length, has an EOT of 10Å, threshold voltage of
|0.25V|, bulk doping of 1.5x1018/cm-3(NA), source drain doping of 1.15x1019/cm-3(NSDE)
27
and the deep source drain doping of 1x1020/cm-3(NS/D). The source drain extension
length is 20nm (LSDE in Figure 3.2) for a spacer thickness of 20nm. All the dopings are
assumed to be uniform and abrupt. Keeping this device as the standard, various device
parameters were tuned. Care was taken to change one parameter at a time so as to identify
the issues related to that parameter easily.
3.4.1 Effect of Gate Oxide Thickness.
Reducing the oxide thickness of the device leads to better gate control of the channel. As the drain current is proportional to Cox to the first order, this would mean that the
time it takes to charge up the capacitor should reduce Tacq, with the scaling up of Cox.
However, the mobility of the device is degraded due to increase in the vertical electric
fields and the increase in the drain current is not linear. In this study since all the devices
were tailored to have a Vt of |0.25V|, the substrate doping of the FET were also increased
as the gate oxide thickness was reduced. This introduces further degradation in the mobility, and hence the drive current. Figure 3.6 shows the variation of the acquisition time,
10
8
520
6
505
490
4
475
2
% Degradation in Tacq
Tacq Acquisition Time (ps)
535
0
9 10 11 12 13 14 15 16 17 18
Gate Oxide Thickness (Å)
Figure 3.6: Acquisition time as a function of the gate oxide thickness, all the
devices had a Vt of |0.25V| and hence the bulk doping varied for the devices.
460
8
28
Droop Rate (Volts/sec)
105
Without gate leakage
Gate leakage included
104
103
102
8
9 10 11 12 13 14 15 16 17 18
Gate Oxide Thickness (Å)
Figure 3.7: Hold voltage droop rate as a function of the gate oxide thickness, all
the devices had a Vt of |0.25V| and hence the bulk doping varied for the devices.
Tacq, with gate oxide thickness, Tox. Reduction in the EOT, increases the drain current
and thus the Tacq decreases. Another point of interest is that the rate, at which the Tacq
decreases, actually degrades, with the scaling down of the EOT. This can be explained
since we realize that there is considerable degradation in the mobility, for small EOTs (the
bulk doping is increased for these devices to keep the Vth at |0.25V|). Also the high vertical fields cause further degradation in the mobilities [35].
Figure 3.7 shows the droop rate for different oxide thickness, with the gate tunneling model on and off. With the gate tunneling model switched off, the characteristics
show a marked improvement with the reduction in Tox. This is because the subthreshold
slope improves as the Tox is reduced leading to smaller leakage currents. The real picture
(red curve) however is quite different. Since the gate tunneling current increases exponentially with the decrease in the Tox, the charge on the storage capacitor finds a leakage path
via the gate electrode. The droop rate increases by orders of magnitude and any sampling
architecture would be severely limited by this problem. For cases where the hold time is
29
pretty large (small sampling frequencies), it is almost certain that the voltage, if sampled
after a long time interval, would be significantly different from the intended value.
The inset in Figure 3.8, shows the amount of charge injected on to the sampling
capacitor when the clock switches to zero volts. The two set of curves correspond to the
hold instances such that the source voltage is either at its maximum (indicated as crest,
Vsource≈0.75V) or its minimum (indicated as trough, Vsource≈0.25V). As shown in [36],
∆V due to charge injection is quite large for small source voltages, whereas the opposite
happens for the gate induced charge injection. Since the channel charge increases as the
gate oxide thickness is reduced, it translates in to a slight increase in the amount of charge
Gate Current off
Gate Current off
Gate Current on
Gate Current on
4.5x10-3
4.0x10-3
3.5x10
∆V due to Charge Injection (mV)
Integral Nonlinearity (volts)
5.0x10-3
-3
6
5
Crest without Gate Leakage
Trough without Gate Leakage
Crest with Gate Leakage
Trough with Gate Leakage
4
3
2
1
0
8
9 10 11 12 13 14 15 16 17 18
Tox Gate Oxide Thickness (Å)
3.0x10-3
INL measured at t=7.5ns
INL measured at t=0.0ns
2.5x10
-3
2.0x10-3
8
9
10
11
12
13
14
15
16
17
18
Tox Gate Oxide Thickness (Å)
Figure 3.8: Integral nonlinearity as a function of the gate oxide thickness, all the devices
had a Vt of |0.25V| and hence the bulk doping varied for the devices. The two time instances
correspond to immediately after and 7.5ns after the clock falls to zero. The second curve
(red triangle) shows enhanced effect of the gate tunneling currents. The inset shows the ∆V
due to charge injection as a function of the Tox. The curves relating to crest and trough correspond to the maximum and minimum source voltage respectively. The charge injection is
severe for the low source voltage case (trough) than for the high source voltage (crest) [36]
30
injected with the scaling of Tox.
Figure 3.8, shows the affect of gate oxide thickness scaling on the Integral Nonlinearity (INL) introduced on to the sampled voltage. The points are obtained by measuring
the maximum difference between the sampled voltage and the applied source voltage at
the end of a clock cycle, for various source potentials. The plots with and without the gate
tunneling current are shown to compare the effect of the gate leakage current. The plots
measured 7.5ns after the clock goes to zero, show enhanced nonlinearity due the gate tunneling current effect. As can be seen, reducing the gate oxide thickness increases the nonlinearity in the sampled voltages. This can be attributed to the increase in the channel
charge injected (inset of Figure 3.8) on the sampling capacitor as the gate oxide thickness
is reduced. Nonlinearity introduced is certainly a very critical issue for sample and hold
circuit, since unlike the offset and the gain errors that can be corrected using differential
circuits and amplifier topologies, the nonlinearity error is hard to compensate.
If we consider the current state-of the art ADC with 12 bit precision and sampling
rate of 50Mhz, the scaling of the gate oxide would be limited to a value of around 12Å or
10Å at best, with SiO2, after which the gate leakage and the INL would become unacceptable. Though some improvement is achieved in terms of the acquisition time with EOT
scaling for a moderate degradation in the injected charge, this advantage is largely offset
by the fact that the leakage currents increase drastically, and any sampled voltage would
be severely degraded even for moderate hold times. Also the nonlinearity introduced for
small gate thicknesses is a critical issue.
31
3.4.2 Effect of Junction Depth:
Another device parameter of interest is the Source Drain Junction depth for a FET.
In order to control the Short Channel Effect (SCE) and the Drain Induced Barrier Lowering (DIBL), it is commonly accepted that Xj should be drastically diminished [37]. On the
other hand shallow junctions lead to an increase in parasitic resistance and involve
increased process complexities to manufacture. This leads to a optimal junction for a
given channel length [38]. As mentioned earlier, in order to decouple the effect of one
process variable, other device parameters were kept constant, while the source-drain junction depth was varied. All the devices in this analysis have a Tox of 10Å and the SDE
length is 20nm (LSDE in Figure 3.2). The bulk doping for all the devices is 1.5x1018/cm3
and the Vt is fixed at |0.25V|. With the increase in the source drain resistance (as Xj is
scaled down), the delay of charging the sampling capacitor increases which translates into
700
50
Tacq for different junction depths
650
600
40
30
550
20
500
10
450
400
7
0
11 13 15 17 19 21
Junction Depth (nm)
Figure 3.9: Acquisition time as a function of
the source drain junction depth, all the
devices have a Tox of 10Å and a Vt =|0.25V|.
% Degradation in Tacq
Tacq Acquisition Time (ps)
an increase in Tacq. This can be seen quantitatively in Figure 3.9. The case with and with-
CLK
RSD
RSD
Vin
Vbias
Vout
VD
VS
V’D
V’S
CLK
9
Figure 3.10: Equivalent circuit, with parasitic source-drain resistance. The pass gate
is turned “On”, with both NFET and PFET
conducting. The input voltage source is
ideal with zero input resistance.
32
Droop Rate (Volts/sec)
105
104
Droop Rate without Gate Leakage
Trough without Gate Leakage
103
102
7
9
11
13
15
17
19
21
Junction Depth (nm)
Figure 3.11: Hold voltage droop rate as a function of the source drain
junction depth, all the devices had a Vt =|0.25V| and a Tox of 10Å.
out the gate tunneling model did not differ much, which is due to the fact that with the
device in the conduction mode, the drain current is several orders of magnitude larger than
the gate current. As Xj is reduced the parasitic source resistance RS increases, this
increases the RC charging time of the sampling capacitor (Figure 3.10). Moreover,
although the over drive ( V GS – V T – mV DS ⁄ 2 ) of the FETs remains the same [39], there
is a drop in the source drain voltage ( V ' DS = V DS – 2 × I D × R SD ) with the increasing
RSD, and since the FETs are in triode, this translates to a reduced IDRAIN. The rise in the
Tacq is thus almost quadratic as can be seen in Figure 3.9 and increases quite rapidly as the
junction depth is reduced.
Figure 3.11 shows the sampled voltage droop rate for various junction depths. The
fall in the droop rate is due to the enhanced source drain resistance which reduces the gate
leakage current. For shallow junction depths, the voltage drop across the resistor RSD
reduces the magnitude of VGD and hence the gate tunneling current effect is further miti-
33
∆V due to Charge Injection (mV)
6.0
5.0
4.0
Crest without Gate Leakage
Trough without Gate Leakage
Crest with Gate Leakage
Trough with Gate Leakage
3.0
2.0
1.0
7
9
11
13
15
17
Junction Depth (nm)
19
21
Figure 3.12: ∆V due to charge Injection as a function of the Xj, all the devices have
a Vt of |0.25V|. The curves relating to crest and trough correspond to the maximum
and minimum source voltage respectively. Note how the charge injection is severe
for the low source voltage case (trough) than for the high source voltage (crest) [36].
gated. This can be seen by the change in the slopes for droop rate with gate leakage (red
curve), below 13nm, wherein the gate tunneling current starts to reduce by the two mechanisms.
In Figure 3.12, we can see the effect of varying the junction depth on the charge
injection voltage onto the sampling capacitor. For shallow junction depths, the channel
current is reduced and so is the injected charge. Gate leakage current does not affect the
injected charge to a great extent, at least for the chosen device parameters in this analysis
The design of the junction depth is constrained by the maximum source drain
resistance that a circuit can tolerate. Reduction in the droop rate is traded-off with the
increase in the Tacq; reducing the Xj from 20nm to 8nm increases the Tacq by 46.6%
whereas the droop rate reduces by 98% and the charge injection by 11%. ∆V due to charge
injection, is really not a major issue with the scaling of junction depths. For channel
lengths of 50nm, the drain SCE effect will also modulate the subthreshold leakage current.
34
Deeper drain junction will modulate the channel barrier to a greater extent and increase
the leakage current in few bias cases (high drain bias FETs will have higher DIBL). With
decreasing channel lengths this effect is expected to worsen with deeper junction depths.
Thus in designing the source and drain depth, we would still like to reduce the SD depth
by as much as possible by the manufacturing process.
3.4.3 Effect of Source Drain Extension Length:
The source drain extension length defined by dose and energy of the source drain region
implant plays a very important role in defining the electrical properties of the MOSFET.
Effect of source/drain extension (SDE) length was studied comprehensively for
Lgate≈100nm regime [38] and it was believed that a SD overlap length of approximately
20nm is necessary prior to the onset of rapid Ion degradation for conventional implant
devices. However recent studies have shown that Ion degradation with small gate overlap
mainly comes from the SDE region under the sidewall spacer due to its graded low doping. Box like S/D junctions, as applicable to this simulation study, show that SDE-to-gate
overlap can be eliminated to a great extent without the degradation of Ion with correct S/D
design [40]. The simulated structure, with the SDE length defined, is shown in Figure
3.13. We define the SDE length, length of the low doped shallow junction, to be zero for
the point where the gate electrode and the side wall spacer meet, Figure 3.13. Thus for a
0‹SDE‹5nm we have an overlap condition and for -5‹SDE‹0 nm we have the under-lapped
MOSFET junction. In all these devices the Tox was fixed at 10Å, and the SDE junction
35
Lgate
20nm
Tox
n+ poly Gate
13nm
Rsh
Rco
Rac
Lmet
Underlap Overlap
30nm
Deep SD Region
-5
0 +5
SDE Source Drain Extension Length
Figure 3.13: Dimensions of the various junctions and the source drain
extension length. Note that all the profiles are uniform box profiles.
depth was kept fixed at 13nm, as specified by the ITRS, for a 50nm gate length. Vt for all
the devices was fixed at |0.25V|.
Figure 3.14, show the variation of the Tacq with the SDE length. As for the case of
decreasing junction depth, reducing the SDE length, increases the channel to source and
channel to drain resistances. Of the various components of the channel to electrode resis-
700
60
650
50
600
Tacq for different SDE
40
550
30
500
20
450
10
400
-5 -4 -3 -2 -1 0 1 2 3 4
Source Drain Extension (nm)
5
% Degradation in Tacq
Tacq Acquisition Time (ps)
tance, like the accumulation resistance (Rac), the spreading resistance (Rsp), and the con-
00
Figure 3.14: Acquisition time as a function of the SDE length, all the devices
have a Vt of |0.25V| and similar Tox and Xj of 10Å and 13nm respectively.
36
Droop Rate (volts/sec)
106
105
104
103
Droop Rate without Gate Leakage
Droop Rate with Gate Leakage
102
-5 -4 -3 -2 -1 0 1 2 3 4 5
Source Drain Extension (nm)
Figure 3.15: Hold voltage droop rate as a function of the SDE length, all the
devices have a Vt of |0.25V| and similar Tox and Xj of 10Å and 13nm respectively.
tact resistance (Rco), it is the Rac that is being modulated in this case (Figure 3.13). The
decrease in the SDE length, increases the resistance as well as reduces the drive voltage
(VDS), and thus Tacq increment with reduction in the SDE length is very rapid for negative
values of SDE lengths.
If we concentrate on the variation of the hold state voltage droop rate (Figure
3.15), we realize that gate tunneling has a very severe effect on it. The droop rate is
extremely high (≈106V/sec.) for the case of SDE=5nm, this is much larger than the
observed values for the case of minimum oxide thickness (Tox=8Å) or maximum junction
depth (Xj=20nm) both of the order ≈9x104V/sec. Also the slope of droop rate vs. the SDE
length is very high, indicating that the droop rate is a strong function of the SDE length.
The reason behind such high sensitivity of the gate tunneling current on the SDE length is
explained in Chapter 2, where it is shown that the predominant gate tunneling current path
during the hold mode is via the gate-source overlap region. Figure 3.16 shows the Ion
variation, which is in agreement with the variation in the Tacq. Figure 3.17 shows the vari-
37
5x10-7
NFET Gate Current (Amps)
0.0060
Ion (Amps)
0.0050
0.0040
0.0030
Ion for PFETs width=20µm
Ion for NFETs width=10µm
0.0020
0.0010
-5 -4 -3 -2 -1 0 1 2 3 4 5
Source Drain Extension (nm)
Figure 3.16: On current of the pass gate, for
NFET and PFET. Bias voltages are Vs=Vb=0
and Vg=Vd=1.0Volts, all the devices have a
Vt of |0.25V| and similar Tox and Xj of 10Å
and 13nm respectively.
4x10-7
3x10-7
Igate for NMOSFETs
width=10µm
2x10-7
1x10-7
0x10-7
-5 -4 -3 -2 -1 0 1 2 3 4 5
Source Drain Extension (nm)
Figure 3.17: Gate current of the NFET. Bias
voltages are Vs=Vb=Vg=0 and Vd=1.0Volts,
all the devices have a Vt of |0.25V| and similar Tox of 10Å and Xj=13nm. The PFET gate
tunneling current was an order of magnitude
smaller than the NFET gate tunneling current.
ation of the gate current with the SDE length. The increase in the SDE length reduces the
source drain resistance, increases the overlap region (area for gate tunneling current), the
overlap capacitance and also increases the potential difference between the drain and gate,
due to reduced voltage drop across the RSD (Igate is exponential function of this potential). Thus the gate tunneling current increases very rapidly when the SDE length is
increased [41].
The inset in Figure 3.18 shows the variation of the injected charge with the SDE
length. Results for the trough case are on the expected lines, with the charge injection
reducing with the reduction in the SDE length, as the total channel current and charge
degrade. The point of interest is the case of long SDE, in the crest region. There is a
marked difference between the case of the charge injected voltage, with and without gate
tunneling, a characteristic that was not observed earlier. The gate tunneling current is
38
∆V due to Charge Injection (mV)
5.0
Integral Non Linearity (mVolts)
4.5
4.0
5.5
4.5
Crest without Gate Leakage
Trough without Gate Leakage
Crest with Gate Leakage
Trough with Gate Leakage
3.5
2.5
1.5
0.5
3.5
-5 -4 -3 -2 -1 0 1 2 3 4
Source Drain Extension (nm)
5
INL measured at t=7.5ns
INL measured at t=0.0ns
3.0
Gate Current off
Gate Current off
Gate Current on
Gate Current on
2.5
2.0
-5
-4
-3
-2
-1
0
1
2
Source Drain Extension (nm)
3
4
5
Figure 3.18: Integral nonlinearity as a function of the SDE length. All the devices had a
Vt =|0.25V| with similar Tox=10Å and Xj=13nm. The two time instances correspond to
immediately after and 7.5ns after the clock falls to zero. The second curve (red triangle)
shows enhanced effect of the gate tunneling current. The inset shows ∆V due to charge
injection as a function of the SDE. The curves relating to crest and trough correspond to
the maximum and minimum source voltage respectively. The charge injection is severe
for the low source voltage case (trough) than for the high source voltage (crest) [36].
reducing the effect of the channel injected charge, especially for the case of Crest. To
understand this, we realized that since the PFET has twice the width as the NFET, the net
charge injection is positive in magnitude (net clock feed trough and channel charge is positive). The tunneling current of the NFET, draws the charge deposited on the sampling
capacitor out of the gate electrode and thus it acts to restore the additional charge deposited on the capacitor by the pass gate. This phenomenon is exemplified for the case of a
long SDE length since the NFET gate tunneling current is now significant and can easily
counter the effect of the injected voltage by the pass gate.
39
Figure 3.18, shows the variation of the INL with the SDE. We observe that the INL
increases with increase in the SDE length. This can be again explained using the fact that
since the overlap capacitance increases with SDE length, the charge deposited on the sampling capacitor and hence the nonlinearity increases. The nonlinear junction capacitance
and the overlap capacitance resulting from the source/drain and gate electrode overlap of
the pass gate leads to a nonlinear charge-to-voltage conversion. This is because the charge
stored on the junction capacitance, Cj, in not equal to Vin0Cj, but rather equal to
V in0
q cj =
∫
C j dV
0
Since Cj is a function of the voltage, qcj exhibits a nonlinear dependence on Vin0, thereby
creating a nonlinear component at the output, after the charge is transferred to the storage
capacitor [42]. In this case there is a marked increase in the INL for the case of nonlinearity measured 7.5ns after the hold cycle. The extremely high gate tunneling currents are
responsible for the high INL at these SDE lengths. Unlike the previous case (Figure 3.8)
when there was little difference between the INL with and with out the gate leakage for
t=0ns, in Figure 3.18 we observe that there is a visible degradation in the INL even at
t=0ns. This again is due to the high gate tunneling current that flows through the overlap
region, for long SDE lengths.
The SDE length plays a critical role in the design of the sample and hold circuit.
For a moderate decrease in the Ion (13%) with the reduction in the SDE length from (5nm
to 0nm), we can achieve a reduction in the gate leakage current of the order of 83%. This
would not only reduce the droop rate by an order of magnitude (from ≈5x106 to ≈5x105)
but also reduce the injected charge and the nonlinearity, circuit parameters that are very
40
hard to compensate otherwise. This reduction in the SDE length would certainly increase
the acquisition time (11% increase), but this can be traded-off with the benefits that are
obtained otherwise.
3.4.4 Gate Length Scaling:
Given the analysis in the previous sections, the reasons to scale FETs in a pass gate
must be revaluated. If we are able to achieve better S-H circuits performance, with larger
gate lengths and with thicker gate oxides, there is certainly no merit in using scaled MOSFETs. To test this hypothesis, the S-H circuit performance of the CMOS pass gate for different gate lengths is evaluated.
Figure 3.19, shows the acquisition time, Tacq, for three different gate lengths with
the gate oxide and junction depths, scaled in accordance to the ITRS guidelines, for corre-
4.0
Tox=13Å
Tox=15Å
Tox=18Å
700
600
500
400
Tox=13Å
Tox=15Å
Tox=18Å
3.5
INL (mVolts)
Acquisition Time (ps)
800
3.0
2.5
2.0
50
60 70 80 90
Gate length (nm)
1.5
100
50
60 70 80 90
Gate length (nm)
100
Figure 3.20: INL vs the gate length for
devices with scaled Tox and a fixed Tox of
15Å. Vdd and Vth were kept fixed at 1.0V
and |0.25V| respectively.
Figure 3.19: Acquisition time vs the gate
length for devices with scaled Tox and a
fixed Tox of 15Å. Vdd and Vth were kept
fixed at 1.0V and |0.25V| respectively.
41
sponding gate lengths. The operating voltage and the threshold voltage were kept fixed at
1.0V and |0.25V| respectively. The storage capacitor was kept fixed at 0.53pF for all the
devices, since for ADCs the size of the storage capacitor is determined by the kT/C
requirements. Other measurement conditions are similar to that in previous Tacq simulations. Also shown in the plot is the gate length scaling trend for a fixed Tox of 15Å but
with other device parameters scaled appropriately. We can see that the scaling does bring
about a reduction in the acquisition time, which means the channel RC delay does play a
significant part in the charging of the storage capacitor. The improvement in the Tacq with
the scaling of Tox for a particular gate length is not significant as is evident from the marginal improvement obtained by using Tox=13Å instead of 15Å for a 50nm gate length and
by using a 15Å gate oxide instead of 18Å for a 100nm gate length.
Scaling of the gate length also leads to improvement in the INL of the pass gate.
Figure 3.20, shows the behavior of the INL for the pass gate for different gate lengths.
These plots were obtained with the gate tunneling model on and the nonlinearity is measured at the instant the clock voltage falls to zero. Plots with the Tox scaled in accordance
with the gate length and a fixed Tox of 15Å are illustrated. We observe that the nonlinearity reduces with the scaling of the gate length. Since the nonlinearity is related to the channel charge deposited on to the storage capacitor, small channel lengths devices inject
smaller amount of charge on the storage capacitor (smaller Lgate/Tox) than longer gate
lengths devices, leading to lower nonlinearity.
42
3.5 Summary:
In this chapter we looked into how the various device parameters of the MOSFET
can influence the circuit parameters of the sample and hold circuit. The effects of the gate
tunneling current can be reduced by choosing a suitably large storage capacitor (low frequency) but since they can not be completely nullified, an understanding of the these
effects is very important. We realize that the scaling of the gate oxide would be severely
limited by the droop rate of the sampled voltage and the non-linearity introduced. This is
fundamentally due to the high leakage currents that degrade the sampled voltage values.
The probable alternative to this issue would be to use high-K dielectric material and gate
electrode with tunable gate work function [43-45]. The source drain junction depth scaling
is still a good option given the various benefits that are obtained in terms of reduced short
channel effects. Such a scaling would ultimately be limited by how shallow junctions can
be manufactured with acceptable sheet resistance. The SDE length is very critical to the
design of the sample and hold circuit. Any amount of unnecessary overlap will increase
the gate tunneling quadratically and has cascading effects on the injected charge, droop
rate and the nonlinearity of the S-H circuit. With uniform box like profiles, best performance would be obtained for the SDE length equal to the spacer thickness. It was also
shown that devices with small gate lengths can operate at a higer frequencies (lower Tacq)
and still have lower nonlinearity, when compaired to longer gate length devices.
43
Chapter 4
Modeling of the Charge Injection in
Sample and Hold Circuits.
4.1 Introduction
After analyzing the effect of gate tunneling on sample and hold circuits, we model the
charge injection induced by the gate leakage current. The error voltage introduced by the
turning off of the MOS switch is one of the fundamental factors limiting the accuracy of
the S-H circuit [46]. This injected charge would not only affect the sampled voltage but
also the nonlinearity of the S-H circuit. This requires an accurate model of the injected
charge. The MOSFET holds mobile charge in its channel when it is “On”, (sampling
mode). When the MOSFET is switched off at the beginning of the hold mode, the channel
charge distributes itself between the drain and the source. The portion of the charge going
into the drain creates an offset in the voltage held by the storage capacitor which is the
sampled voltage. Besides that, the feed through, due to the falling edge of the clock via
the gate drain overlap capacitance also creates an error in the sampled voltage. These
44
effects have been analyzed in detail by [36], [46], and [47-51]. As observed in the previous chapters, the gate tunneling current also affects this sampled voltage. In this chapter
we propose, for the first time, a mathematical model for this sample voltage error, introduced due to the gate tunneling current. The model would be used to identify the various
components of charge injection and the physical phenomenon governing them. The need
for such a model is underlined by the fact that the gate induced charge injection, unlike the
channel induced charge injection, can not be easily compensated by using prevalent circuit techniques. SiO2 despite its high leakage current for thin oxides still continues to be
the dielectric of choice as there are several process and device issues to be resolved before
high-K gate insulator can be introduced. Hence guidelines to control the gate current
induced charge injection are very essential. This model can be used to quickly predict the
worst case charge injection introduced by the gate leakage currents, for a given set of
device parameters and the circuit bias conditions. Finally exact simulation results calibrated from experimental data and the results from the simple analytical model are compared to ascertain the accuracy of the model.
4.2 Analytical Model.
For this study, the capture of channel charges by the interface traps are neglected, also in
this analysis we use a NFET device to illustrate our model; however the discussion is
equally valid for PMOS devices, albeit the magnitude of the gate leakage in a PMOSFET
is a few orders of magnitude smaller than that in NMOSFETs. For the purpose of this
45
model, the switching of the MOSFET can be divided into three distinct phases, depending
on the magnitude of the gate voltage relative to the other electrodes. These different
phases correspond to different charge injection phenomena dominating over each other. In
phase I, the transistor is “On” (VT + VS‹VG ‹VDD) and the channel charge exists from the
source to the drain. When the gate voltage falls below VT, all of the mobile charge exits
through the source and the drain and the channel charge is reduced to zero. A parallel condition exists for the case when the gate voltage falls and lies in the voltage range,
VT‹VG‹VS+VT (phase II). As indicated in Figure 4.1, the edge direct gate leakage current
starts to dominate and for the voltage regime, 0‹VG‹VT, this current component actually
dominates the subthreshold current of the MOSFET (phase III). For very thin gate oxides,
this was already shown in Figure 3.6. As derived in [36] and [48], the KCL law applied
for the NMOSFET and the hold capacitor requires that
dv d
C ox d ( V G – v d )
C L -------- = – i' d +  C o1 + ------- -------------------------
dt
dt
2 
Eq 4.1
Here CL is the storage capacitor, Co1 is the gate-drain over lap capacitance as indicated in Figure 3.5 (given by Cgate-drain), i´d is the drain current flowing through the
MOSFET and vd is the error voltage at the drain end at the time t. As can be clearly seen
this equation does not take into account the change in the storage capacitor voltage due to
the gate current. Such an approximation is fairly accurate when i´d is much larger that the
gate tunneling current, i.e. when the MOSFET is “On”. For extremely scaled gate oxides,
when the gate tunneling current is quite significant, this expression is not completely true.
A more accurate representation of the real situation would require different sets of equa-
46
tions at different bias conditions. If the gate voltage is a constant ramp, which begins to
fall at time t=0 from a value of VDD and reaches a final value of 0V at a constant rate of U
volts/sec, then we can calculate the gate voltage at any instant by the following expression:
V G = V DD – Ut
Eq 4.2
If we assume that the gate voltage ramp rate is much faster than the change in the source/
drain voltage |dVG/dt| » |dvd /dt| the Eq 4.1 simplifies to:
dv d
C ox
C L -------- = – i' d –  C o1 + ------- U

dt
2 
Eq 4.3
In the strong inversion region (VH › VG › VS+VT) we have
i' d = Gv d ≡ β ( V HT – Ut )v d
Eq 4.4
where
W
β = µ C ox ----L
and
V HT = V H – V S – V T
Eq 4.5
thus we have the equation.
dv d
C ox
- U
C L -------- = – β ( V HT – Ut )v d –  C o1 + ------
dt
2 
Eq 4.5
The solution to this differential equation (DE) has the following form
C ox
 C + ---------
πUC L  o1
V HT 2 

 βU
2
 ×
v d ( t ) = – ---------------  --------------------------- exp  ----------  t – ----------
 
CL
2C
2β 
U

 L




erf

β -V
-------------– erf
2UC L HT

β -(V
-------------–
Ut
)

2UC L HT

47
Eq 4.6
This analysis neglects the contribution due to the off-state leakage current of the
MOSFETS. This would be true for most of the sample and hold circuits because once the
gate voltage drops to 0V (clock goes to zero), the source voltage in the worst case is zero,
which implies that the FET is still 0.25V below the threshold. Hence the subthreshold current of the MOSFET can be neglected [36]. In cases where the gate tunneling current
dominates the off-state leakage current, such as in sub-100nm devices, with gate oxides of
the order of a few nanometers, the gate current component also adds to the currents
already flowing in Eq 4.3 and the we would have to solve separate differential equation in
each regime of operation.
(a) While the device is “On” (VS+VT ‹ VG ‹ VDD), the above given solution is
fairly accurate, since the MOSFET drain current is several orders of magnitude larger than
the gate leakage current and Eq 4.3 gives a good representation of the currents. The
charge injected in this phase is obtained by substituting proper limits in the above DE (Eq
4.5) i.e. at t’=VHT/U, the threshold condition is reached and VG=VS+VT. We obtain the
injected voltage in phase I by using Equation 4.6 to obtain
C ox
 C + ---------
πUC L  o1


2
β -V 
v d ( phaseI ) = – ---------------  --------------------------- exp  -------------HT 
CL
2β 

 2UC L



Eq 4.7
(b) Once the gate voltage falls below the threshold voltage, but is still greater than
the source voltage (VS ‹ VG ‹ VS+VT), neither the subthreshold current nor the gate tunneling current (EDT) are significant and the charge injection is primarily due to the gatedrain overlap capacitance. For this phase we can solve the differential equation which
48
simply turns out to be
dv d
C L -------- = – ( C o1 )U
dt
Eq 4.8
C o1
v d ( phaseII ) = – --------- V T
CL
Eq 4.9
and thus
(c)When the gate voltage falls below VS, the Edge Direct Tunneling (EDT) current
dominates the subthreshold conduction of the MOSFET. In this phase there are primarily
two mechanisms for charge injection, first due to the gate tunneling current and the second due to the gate-drain overlap capacitance (the displacement current via the capacitor).
If we neglect the subthreshold current [12] (we already showed in Figure 3.6 that for
Tox=10Å, Ig≈10Isubthreshold) we find that we must solve the following DE.
dv d
I
C L --------- = – ( C o1 )U – ---gdt
2
Eq 4.10
There are several important points to note before we can begin to solve this DE. In
Eq 4.10, we use only half of the total gate current to model the charge injection on to the
storage capacitor. When we write Ig/2, we assume that once the VG falls below VT+VS,
(subthreshold region), the total gate current distributes it self equally between the source
and drain. This can be physically understood by the fact that at the beginning of the hold
state, the source and the drain voltage have roughly the same potential (|dVG/dt| » |dvsource
/dt|) and thus the gate tunneling current shows no preferential behavior for either of these
electrodes. Thus of the total gate tunneling current flowing, only half of it comes from the
storage capacitor which holds the sampled value and the other half arises from the source
side which is not of much significance from the sample and hold perspective. Also the
49
sign of the gate current in this equation is worth taking a note. As already explained in
section 3.2.2, once the gate voltage fall below the source-drain potential, most of the gate
leakage is due to the electrons tunneling through the gate into the source drain region, Fig
3.2 (Edge direct Tunneling). This means that the gate current is flowing into the drain
from the storage capacitor, and going out via the gate electrode. To verify this we simulated a sample and hold circuit with an NMOSFET and plotted the various currents, for
the falling edge of the clock. The polarity of the current is defined such that the current
going into the electrode is positive. As seen in from Fig 4.1, that once the gate voltage
falls below the source voltage (points indicated by arrows in the plot) the sign of the gate
tunneling changes (positive to negative) and this current flows out of the gate electrode.
Also the magnitude and the sign of the drain and source component of Igate is almost the
same for VDrain ≈ Vsource, a fact that can been seen by the overlap of the blue and the
4.0x10-8
Current (Amps/10µm)
2.0x10-8
The time instant corresponds to the falling
edge of the clock. Vsource≈Vdrain≈0.73volts
0.0x10-8
Vgate ‹ Vsource
-2.0x10-8
Total Gate Current
-8
-4.0x10
-6.0x10-8
1.0
Drain Component of the gate Current
Source Component of the gate Current
0.8
0.6
0.4
Gate Voltage (Volts)
0.2
0.0
Figure 4.1: The variation of the various components of the gate current with
the applied gate bias, hold mode starts at Vg≈0.73V, and the drain and source
component of the gate current become equal for the rest of the falling edge.
50
green curves. Having proved that the part of Igate flowing out of the drain is actually half
of the total Igate and negative in polarity, we now move on to actual modeling of the gate
current. In order to model the gate leakage current we adopt the approach used by K.M.
Coa et.al. [52] . What we present here is a simplified model, which is true for the time
interval of interest. i.e. the falling edge of the clock., with out compromising on the accuracy. As reported by Wen-Chin Lee et.al. [53] and confirmed by simulations, the substrate
current generated due to the gate tunneling is very small and matters only in the form of
floating body effects, for SOI devices. The various components of the gate tunneling current are shown in Figure. 4.2. Igso and Igdo are the parasitic tunneling currents through
gate-source/drain overlap region. Igb flows between the gate and the substrate and is negligible in our case. Igc is the gate-channel tunneling current, which is partitioned into Igcs
and Igcd, flowing into the source and drain respectively. Even though it is very hard to
actually differentiate the components of the gate tunneling current in simulations, as
explained in Figure 3.3, for a given the bias condition only one of these components (Igso/
Gate
Source
Igso
Drain
Igcd
Igcs
Igdo
Igb
Figure 4.2: Various components of the gate tunneling current. Igso and
Igdo are the parasitic tunneling currents through gate source/drain overlap
region. Igb flows between the gate and the substrate, and is negligible
[53]. Igc is the gate-channel tunneling current, which is partitioned into
Igcs and Igcd, flowing into the source and drain respectively.
51
Igdo or Igcs/Igcd) dominates. For the bias condition of interest (in our case VG‹VS+VT), it
is primarily the Igso and Igdo, also called the Edge Direct Tunneling currents (EDT) components, that dominate. The EDT in the gate to source/drain overlap region is intrinsically
a two dimensional problem and device parameters like gate oxide thickness, SDE length,
doping concentration, source/drain junction depth and drain bias conditions would affect
the SDE to gate direct tunneling current for short channels devices [54-5]. In order to
model the EDT behavior, MEDICI was used. For conduction band electron tunneling
using the model given by K.F Schuegraf et.al. [56], the direct-tunneling current density
for an oxide voltage, Vox, smaller than the barrier height φb , can be expressed as
J gate
V ox 3 ⁄ 2
 – B 1 –  1 – ------


φ
φ


2φ
2
b
b
= A  --------  --------b – 1 E ox • exp  ----------------------------------------------------
 V ox  V

E ox


ox


Eq 4.11
where,
3
A = q ⁄ ( 8πhφ b )
B = ( 8π 2m ox φ b
3⁄2
⁄ 3hq )
E ox = ( V ox ⁄ T ox )
Tox is the oxide thickness
mox is the effective mass in the oxide
As described in [13] this is just a simplified version of the direct tunneling current
as derived by using the WKB approximation for a trapezoidal barrier. The advantage of
this closed form of equation over the more rigorous approach of solving Airy functions
and numerical double integration as performed in MEDICI, is that we are able to gain an
52
insight into the various device and circuit parameter affecting the gate leakage current. Eq
4.11, has been derived using the WKB approximation for Fowler-Nordheim tunneling,
applied and corrected for a trapezoidal barrier, as is the case for direct tunneling [56].
Though many corrections have been proposed for this equation, to the first order this
equation gives a fairly accurate description of the leakage currents. In order to get an
insight into the physics, we can make some simplifying assumptions to this equation.
Since the EDT current flows in the source/drain overlap region, we will model the gate
current of this region which has a n+ poly gate separated from the n+ source/drain region
via a thin oxide. Fig.4.3, shows the schematics of the band diagram of a n+ polysilicon /
SiO2/n+Si structure showing electron tunneling from the gate to the source-drain extension region for negative gate voltages. Since for direct tunneling, φb » Vox, we can simplify the terms involving Vox/φb in the exponential and in the first term of the gate current
expression in Eq 4.11 to obtain :
– 4πT ox 2φ b m ox
q3 φb
V ox T ox 2m ox
----------------- exp ---------------------------------------- • exp ---------------Jn =
-----------2
qh
qh
φb
4πhT ox
Vox
φb
EF n+poly
φs≈0
φb
EF≈ EC
n+ poly Si Gate
n+ source/drain region
EV
Tox
Figure 4.3: Schematic representation of the band diagram
for the case of a negative bias applied at the n+ poly gate.
53
Eq 4.12
In order to predict the gate tunneling current, an accurate knowledge of Vox is a
must. For NMOSFETs with n+ poly Si gate electrode, the flatband voltage (VFB) at the
heavily doped n+ source/drain overlap region is ≈0V. The expression for the gate voltage
is different from that in the channel region as given in [12] can be written as
V g = V ox + φ s + V FB + V ds
Eq 4.13
here φs represents the voltage drop of the depletion layer of the n+ substrate when a negative voltage has been applied to the gate. As explained above VFB≈0V and for a heavily
doped S/D regions φs≈0V. Since the pass gate is in the process of being turned off, Vd≈Vs,
implying that Vds≈0V. We can thus approximate VG≈Vox to the first order. This greatly
simplifies the equation Eq 4.12 and help us gain insight into the effect of gate leakage on
charge injection. In order to get a better fit between the model and detailed simulations of
MEDICI, we modify Eq 4.12 to Eq. 4.14 using Eq 4.13 and by introduction the fitting
parameters α, β and γ that have defaults of 0,1 and 1 respectively.
3
– 4πT ox 2φ b m ox
q φb
– V G γT ox 2m ox
- exp ---------------------------------------- ------------ β • exp ----------------------J n = α – ----------------2
qh
qh
φb
4πhT ox
Eq 4.14
The values of mox, mass of electron in the oxide is 0.4mo, where mo is the mass of free
electron (obtained from the overall best fit [53]) and the barrier height φb, is 3.15eV. Now
that we have an expression for the gate leakage current density, we can begin with the task
of modeling the charge induced by the gate leakage current. We have to solve the DE
given by Eq 4.10. The values of the overlap capacitances, Co1, were obtained by detailed
54
simulations in ATLAS. Finally solving the DE, we get the following expression for the
charge injected during the period over which the gate voltage falls from VS to zero.
V S ⋅ X – YZ C o1 V s
∆V D = -------------------------- – --------------U ⋅ CL
CL
Eq 4.15
where X, Y and Z are given as follows:
X = α
3
– 4πT ox 2φ b m ox
q φb
- β
- exp ---------------------------------------Y = ----------------2
qh
4πhT ox
φb
qh
Z = ---------- ----------γT ox 2m ox
Summing up the various components of charge injection, namely the charge injection due to (a) the drain current, (b) the clock feed through via the gate over lap region and
(c) that due to the gate tunneling current, we can get the expression for the total charge
injected due to the falling edge of the clock. In order to express the erf of Eq 4.6 in simpler
form we realize that
1


2
erf ( x ) ≈  2x 
x-----
-----1
–
 
3
 π
Thus for slow switching-off case i.e.
2
βV HT
U « -----------2C L
Equation 4.6 reduces to the form:
55
if
x»1
if
x«1
ox
C + C
------ o1
Y ⋅ Z – X ⋅ VS
2 - πUC L C
o1
----------------------vd = 
 --------------- + --------- ( V S + V T ) + ------------------------------CL
CL 
2β
U ⋅ CL



vchannel charge
vclock feed through
Eq 4.16 (a)
vgate current
and for fast switching when the condition
2
βV HT
U » -----------2C L
is satisfied, Equation 4.6 takes the form
ox
C + C
3
------ o1
βV HT  C o1
Y ⋅ Z – VS ⋅ X
2 
v d =  ------------------------  V HT – ------------- + --------- ( V S + V T ) + -----------------------------CL  
U ⋅ CL
6UC L C L



vchannel charge
vclock feed through
Eq 4.16 (b)
vgate current
In Equation 4.16a,b, we have identified the various components of charge injection, namely the charge injection due to channel charge, due to clock feed through and due
to the gate current. One of the assumption that was made in the formulation of these
model was that the junction capacitance did not change significantly with the turning
“On” of the gate tunneling current and the values remained the same as they were with the
gate tunneling current turned off. This is true because the small magnitude of the current
is insufficient to change the depletion region widths. This model helps us look beyond the
simulation results as given by MEDICI, since it helps us distinguish between the various
components of charge injection namely due to the channel charge, due to the clock feed
through and that due to the gate current injection.
56
Having constructed a model to estimate the components of charge injection, in the
next section we evaluate the utility and accuracy of such a model. The proposed model is
based on physical derivation and requires very few fitting parameters. This model is especially very important when we realize that physically it would be very hard to separate the
individual components of charge injection. The advantage of this model over simulations
is that besides beign able to identify each component affecting the charge injection, we
can give a design guideline as to which component is expected to dominate for a given set
of device parameters.
4.3 Results obtained from the Model.
In this section we simulate a set of devices with varying process and circuit conditions and compare the results as predicted by the analytic equation Eq. 4.16 (a) and Eq.
4.16 (b) with those of detailed numerical solution as given by MEDICI.
4.3.1 Simulation Setup
The first set of devices that were modeled were that of varying source/drain overlap lengths. The reason that such kind of devices were chosen was that during the fall of
the clock voltage, the contribution to the injected charge due to gate leakage is predominantly due to the EDT which flows in the source/drain overlap region. The amount of gate
leakage varies with the variation in the overlap length and this can be used to see if the
analytic model is able to correctly predict the effect of process parameter variations on the
gate leakage current. Like the simulations in chapter 3, these simulations were performed
57
Vg
Gate
Vs
Deep S/D
Depth
Tox
Vd
Vin
NFET
Source Drain
o
Xj
Source
Lg
LSDE
NA
0.25Sinωt 0
NS/D
Drain
Vout
Storage
Capacitor
0.5V
NSDE
Clock
Figure 4.4: Device structure and circuit topology considered for the model.
using the Mixed-Mode Utility of MEDICI. In this study, for the modeling of charge injection, we used pass gates composed of just the NFET, because it was easier to analyze the
effect on gate current in the presence of a single majority carrier. These results would be
equally true for PMOS devices. The basic structure used in the simulations is shown in
Figure 4.4. Gate lengths of 50nm and oxide thickness Tox of 1.0nm were considered. The
source drain extension (SDE) depth was fixed at 13nm, as per the ITRS specifications for
50nm gate length. According to ITRS, for gate lengths of 50nm, metal gate electrodes
would be introduced, but a sizable part of recent research is still based on poly Si gate
electrodes [27-30]. This is due to the fact that the choice of metal with a suitable workfunction is still an active research field work and it will take some time before it is introduced as an industry standard. Thus for the purpose of this study we have chosen doped
poly Si as the gate electrode material. Substrate doping was fixed at 1.5x1018/cm3 (for the
case of varying Tox, this was varied from 7.5x1018/cm3 to 1.5x1018/cm3, p-type), this
insured that for a n+ poly gate, the threshold voltage for the devices is roughly 0.25V.
SDE doping of 1.15x1019/cm3, deep source/drain depth of 30nm and doping of 1x1020/
cm3 (n-type) are kept constant for all the devices. The clock voltage applied at the gate of
58
MOSFET has a maximum of 1V. The voltage to be sampled, applied at the source of the
MOSFET is a 0.5V (peak to peak), sinusoid in series with a 0.5V DC signal. The small
value of the AC signal is chosen so that the N-MOSFET is always operated in turn-on
region, when the clock is non zero. Also with large source voltages there were convergence issues which could be circumvented by using small source voltages, while keeping
the essential physics the same. The frequency of the AC signal applied to the input of the
pass gate is 2Mhz. This was chosen sufficiently high to ensure that the overlap and junction displacement currents also form an important part of the entire analysis, as it happens
in real circuits. Similar to actual circuit situation, the substrate of the NMOS is connected
to the GND. The clock used for all the simulations has a period of 300ns and a realistic
droop rate of 5ns. The duty cycle of the clock was 50%. Uniform doping profiles and
abrupt junctions are assumed in all regions. Also, due to the lack of simulation models the
impact of various device parameters on noise and mismatches due to random fluctuations
is not studied. For the model, the sampling instance was chosen such that the
Vsource≈0.75V; which is the case of worst case gate current induced injection.
4.3.2 Variation of Components with Source Drain Extension Length
We define the overlap (OL) length as the length of the low doped shallow junction
from the point where the gate electrode and the side wall spacer meet, Figure 3.14. An OL
length of 0nm would correspond to a SDE length of 20nm. Thus for a 0‹OL‹5nm, we have
an overlap condition and for -5‹OL‹0 nm we have an under-lapped MOSFET junction.
The overlap length was varied from 0nm to 5nm, keeping the Lgate fixed at 50nm, implying that the effective channel length, (Leff) would actually vary for different OLs. The
59
value of overlap capacitances as extracted by device simulation and used in the model are
given in the table Table 4.1 below.
Device
Coverlap S/D(fF)
Cox (fF)
OL length 0nm
17.5fF
3.49fF
OL length 1nm
17.5fF
3.60fF
OL length 2nm
17.5fF
3.70fF
OL length 3nm
17.5fF
4.04fF
OL length 4nm
17.5fF
4.30fF
OL length 5nm
17.5fF
4.73fF
Table 1: Overlap capacitance for different SDE lengths
Since these values are obtained using detailed simulations, they include the effect
of the various fringing fields. Also because the exact overlap capacitance values vary with
the gate voltage these values were obtained as an average over the range. These extracted
values are used to model the charge injection both due to the channel charge and the gate
tunneling currents. Once we have the overlap capacitance, it is used to get the area via
which the gate leakage current would flow, (recall that earlier we had derived an expression for the gate current density). In order to verify the validity of the model, we performed mixed-mode simulations with and without the gate tunneling model. This allowed
us to identify and quantify the effect of the gate tunneling current on charge injection. As
we shall see, the charge injection due to the gate tunneling current does contribute significantly to the injected charge on the sampling capacitor.
In the Figure 4.5 we plot the voltage change in the sampled voltage due to individual contributions of the components of charge injection, with the variation in the SDE
60
length. A significant contribution to the total charge injection is due to the clock feed
through. As the OL length increases and there are several adverse phenomena affecting
the components of the charge injection. Firstly, as the overlap capacitance increases, the
effect of clock feed-through increases, secondly the contribution of the gate tunneling currents, which flows via the overlap region, increases. With the increase in the OL length,
the resistive voltage drop across the source/drain resistor RSD reduces and hence the difference in the gate-drain potential increases. This leads to an exponential increase in the
gate tunneling current. As predicted by Eq 4.16(b), the both the clock feed through
induced and the channel charge induced charge injection increase with increase in Co1.
The channel charge component of injection increases only marginally with the increase in
the OL length. For the case of zero or small overlap, the gate induced charge injection in
|∆V| due to Charge Injection (mVolts)
relatively small and its the components due to the clock feed through and the channel
101
100
Points: Data from Simulations
Lines : Data from Model
10-1
10-2
0.0
Total Charge Injection
Clock feed through induced
Channel charge induced
Gate Current induced
1.0
2.0
3.0
4.0
Over Lap Length (nm)
5.0
Figure 4.5: Charge injection voltage due to the three major components of
charge injection as predicted by the model (solid line) and as obtained by
detailed simulations (solid squares). The source voltage is 0.73 volts and the
droop rate is 2x108V/sec. Capacitance values were taken from the Table 4.1.
61
charge that contribute to the over all charge injection. Channel charge induced charge
injection, can be compensated by the use of pass gate composed of a NMOS and PMOS
FETs and the clock feed through effect that can be compensated via a dummy transistor,
hence for small OL length, most of the charge injection can be compensated. As the OL
length increases the gate current increases rapidly and for OL lengths of 4nm and higher,
the two major contributors to the total charge injection are clock feed through and the gate
induced charge injection. Such a case is of serious concern, since it would be very hard to
compensate the ∆V due to gate leakage, using conventional circuit techniques because of
the inherent imbalance in magnitude between the gate leakage current in a NFET and
PFET.
Also shown in the Fig 4.5, are the values of gate induced charge injection as
obtained from simulations and the model. As can be seen, there is quite a good match
between the results predicted by the detailed MEDICI simulations and that obtained from
the analytic model in Eq 4.16b.
We see that the gate tunneling current is indeed a serious issue especially for 50nm
devices, when the gate to source/drain overlap region can be relatively a large fraction of
the channel length. A brief note on the magnitude of the numbers. A 12 bit ADC operating
at 1V power supply, has a LSB that corresponds to an analog voltage of 0.24mVolts, this is
significantly smaller than the error introduced by the gate current induced charge injection, which is of the order of 1mV for an OL length of 5nm.
62
4.3.3 Variation of Component with Gate Oxide Thickness
To further test the validity of the model with respect to other device parameters we
model the gate current induced charge injection for various oxide thicknesses as well.
Again using the model we are able to obtain the magnitudes of the various charge injection
components. All these devices have a fixed SDE length of 22nm (the OL length is 2nm)
and the junction depth is fixed at 13nm. Substrate doping is varied from 7.5x1017/cm3 to
1.5x1018/cm3 (p-type). This ensured that for a n+ poly gate, the threshold voltage for the
devices was roughly 0.25Volts. To validate the accuracy of the model, we compare the
total and the gate current induced charge injection as obtained from simulations and
model. In simulations we separate the effect of the gate current from the channel charge
and clock feed through, by comparing the results with and without the gate tunneling
|∆V| due to Charge Injection (mVolts)
model.
101
100
Total Charge Injection
Clock feed through induced
Channel charge induced
Gate Current induced
10-1
10-2
10-3
10-4
10-5
Points: Data from Simulations
Lines : Data from Model
8
9
10 11 12 13 14 15 16 17 18
Gate Oxide Thickness (Å)
Figure 4.6: Charge injection voltage due to the three major components of charge injection as predicted by the model (solid line) and as obtained by detailed simulations (solid
squares) for various oxide thicknesses. The OL length and junction depth are kept fixed.
63
Once again the main contribution to the total charge injection is due clock feed
through. The components of channel charge and gate current induced injection are fairly
small in comparison. The exponential dependence of the gate tunneling current on the gate
oxide thickness, dictates that the charge injection due to the gate tunneling current
increases very rapidly as the gate oxide is reduced. For the components of channel charge
and clock feed through the dependence of charge injection on Tox is roughly linear (Eq
4.16a,b). For the thicker gate oxides the charge injection due to gate leakage is a nonissue
since the gate tunneling current is very small. This can be clearly seen in Fig 4.6. For the
case of Tox=8Å, the gate current induced injection voltage is small (0.06mV) when compared to the other injection components, this is because of the small OL length. This
would not be the case for moderate OL lengths, the gate induced injection voltage would
be quite significant for thin gate oxides. Again a good fit between the analytic model and
detailed simulations is seen.
4.3.3 Variation in components with Clock Droop Rate
Having tested the basic modeling of the gate leakage current by varying the device
parameters of Jgate tunneling, we verify the validity of the Eq 4.16a,b, in terms of varying
circuit parameters. The oxide thickness for all these devices is 10Å and the SDE length is
22nm (OL length is 2nm). In Fig 4.7 we have plotted the charge injection voltage due to
its various components versus the clock fall rate U. All these cases correspond to fast
switching and Eq 4.16b is used to model the gate induced charge injection. The clock fall
rates are varied from 4ns to 20ns for a 1V drop (gate voltage). Also to ensure similar injection conditions for all the cases, it was made sure that average source voltage remained the
64
|∆V| due to Charge Injection (mVolts)
101
100
10-1
0.05
Total Charge Injection
Clock feed through induced
Channel charge induced
Gate Current induced
Lines : Data from Model
Points: Data from Simulations
0.10
0.15
0.20
Droop Rate (Volts/ns)
0.25
Figure 4.7: Charge injection voltage due to the three major components of charge
injection as predicted by the model (solid line) and as obtained by detailed simulations (solid squares) for various clock droop rates. The gate oxide thickness and the
OL length are kept fixed. Average source voltage is the same for all the devices.
same for all the cases. In order to achieve this we make the simplifying assumption that
|dVG/dt| » |dvd /dt| and by shifting the instant of clock fall with the variation in the fall
rates, the average source voltage for all fall rates was maintained the same.
We again observe that the clock feed through component of the charge injection
dominates the total charge injection. At a droop rate of 0.13V/ns the gate induced charge
injection exceeds the channel charge contribution. As predicted by Eq 4.16(b) the clock
feed through component is relatively independent of the droop rate, where as the channel
charge injection reduces with the reduction of the droop rate. Figure 4.7 has a physical
explanation because the amount of time over which the gate current is injected, increases
as the fall rate is reduced. Thus for a fall rate of 0.05V/ns, it would actually take 20ns for
the gate voltage to drop to a zero value. The time over which the gate current is injected
(Vg ‹ Vs) and thus the injected charge, would be significantly higher for this case versus
65
the case when the entire gate voltage drops to zero in 4ns (fall rate =0.25V/ns). Again a
good correlation exists between the values of charge injection as predicted by the model
and the detailed device simulations. The dependence of the injected voltage to the fall rate
is nearly 1/U, as predicted by the model (Eq 4.16a,b).
4.4 Summary
In this chapter we have proposed a charge injection model that incorporates the
effects of gate leakage current. The effects of the gate tunneling current can be reduced by
choosing a suitably large storage capacitor or by increasing the frequency of operation (Eq
4.16 a,b), but since they can not be completely nullified, an understanding of the various
parameters that influence the gate induced charge injection is very important. Such a
model would be very relevant, for scaled CMOS circuits, especially if we realize that the
gate tunneling current would be a major issue for the 65nm technology node and its affects
are hard to compensate using conventional circuit techniques. Using the model, we were
able to identify the individual contribution due to the clock feed through, the channel
charge injection and the gate current induced charge injection, which otherwise can not be
differentiated using device simulator. Also the dependence of device parameters on these
components was obtained, which could be used to tailor individual components of charge
injection. The model was verified by comparing the results between the model and device
simulations, with varying the circuit parameters like clock fall rate and device parameters
like the SDE length, gate oxide thickness.
66
Chapter 5
Conclusions
5.1 Summary
The recent interest in integrating analog and digital blocks on the same chip for
mixed mode applications demands better understanding of the device characteristics of
bulk MOSFETs. Sampling circuits, an essential part of the ADCs, act as an interface
between the analog world and the signal processing digital systems and hence must match
the performance and speed of the overall system. The motivation behind this work was to
analyze the performance of the sample and hold topology composed of sub-65nm bulk
MOSFETs and to analyze the various trade-offs that exist among the constituents of performance metrics. Device parameters like the oxide thickness, bulk doping, source drain
overlap region and the junction depth were optimized to obtain the best operation for the
sampling circuit.
In order to gain insight into the operation of the sample and hold circuit, detailed
simulations were carried out with incorporation of accurate gate tunneling current models.
67
The key performance parameters were identified and an understanding of the physics
behind the relation between the performance metrics and the device parameters was developed. It was observed that scaling Lgate improved the sample and hold circuit metrics by
reducing the Tacq and simultaneously reduced the nonlinearity. We observed that if the
gate oxide was scaled in accordance to the ITRS requirements, although an improvement
in terms of reduced Tacq was obtained, other performance measures like the droop rate and
the nonlinearity degraded. The excessive gate tunneling current and the reduced mobility
(to keep the Vt fixed, the doping was increased) had a major role in this behavior. Scaling
of Xj also has conflicting requirements for the Tacq and the nonlinearity. It was shown that
since the Xj scaling had only a minor effect on the trade-offs, it should be set by constrains
dictated by the ease of fabrication. One very critical parameter identified by this study for
a FET in a pass gate, was the source/drain overlap length. It was shown that with marginal
improvement in operation frequency, the nonlinearity and the droop rate could increase
dramatically for FETs with large overlap regions. While the exact values of performance
metric constituents might vary with fabrication, the trends and percentage changes are
expected to be the same as presented in this study.
We can conclude that for a sample and hold circuit, we would like reduce the junction depth and the source/drain overlap region, but keep the Tox as thick as permitted, for
a given channel length. Though many of the design requirements are defined by circuit
specifications, these device guidelines can be used to improve the sample and hold operation to a fairly general degree.
68
Another issue that was addressed in this study was the gate induced charge injection. Charge injection due to the channel, clock and the gate leakage current contributes to
the nonlinearity of the pass gate and hence an accurate estimate of total charge injection is
very important especially for high precision ADC. We have extended the charge injection
model of Ben Sheu et al. to incoporate the influence of the gate tunneling current. The
model includes device parameter dependence of these components, so that individual
components can be tailored. This should be quite helpful to circuit designers in the first
order design of a sampling circuit and to implement various strategies to reduce the charge
injection.
5.2 Future Work
This work concentrates on the performance of sample and hold circuits composed
of sub-65nm devices. Although various issues were extensively addressed, this study is
no way exhaustive. To begin with, although sample and hold blocks are an important part
of System on Chip (SOC), there are however various other analog blocks that need to be
considered in terms of their scaling. Blocks such as a single stage differential amplifier,
PLL circuit, power amplifier and other basic analog circuit blocks could be evaluated in
terms of their performance metric dependence on the device parameters. Such a study
would give a big picture in terms of improving the operation of the over all system. Since
this study was based on simulation results, further work needs to be done to analyze these
effects in fabricated devices and support the results presented here.
69
In this work we concentrated on the performance of a circuit composed of deeply
scaled bulk MOSFETs. For logic applications other technologies like silicon on insulator
(SOI) and double gate (DG) MOSFETs are under active research for sub 0.1µm devices.
The circuit performance of these devices can be studied in similar details and thus the performance of various technologies being considered for digital performance enhancement,
can be compared. This would give leads to which technologies should be used for mixed
mode applications in the future.
It has been shown in this study that for sub-65nm regime CMOS, the gate leakage
current would be a very critical issue in the entire design, if SiO2 is used for the gate
dielectric material. High-k gate insulators can reduce the gate tunneling current dramatically but they also reduce the channel mobility of the FETs. A study on the merits of
devices with high-k gate dielectric would be quite interesting to see how the various circuit metrics are affected by the use of high-k. Also the performance of the S-H circuit at
high frequencies (few Ghz) would be an interesting study, as to how the performance metrics are affected.
70
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