MINISTRY OF SCIENCE AND TECHNOLOGY
DEPARTMENT OF
TECHNICAL AND VOCATIONAL EDUCATION
Sample Questions and Worked Out
Examples
For
Ece-03011
DIGITAL DESIGN
B.Tech (First Year)
Electronic Engineering
CHAPTER-1
Introductory Digital Concepts
* 1.
Name two advantages of digital data as compared to analog data.
**2.
Determine the (i)period of waveform (ii) frequency (iii) duty cycle in figure.
V
0
t (ms)
1
3
5
7
9
11 13
15
17
***3. Which is thetotal serial transfer time for the eight bits in figure? What is the total
parallel transfer time?
0
* 4.
1µs 2µs 3µs 4µs
5µs
6µs
7µs
8µs
Consider a register that can store eight bits. Assume that it has been reset so that it
contains zeros in all positions. If you transfer four alternating bits (0101) serially into
the register, beginning with a 1 and shifting to the right, what will the total content of
the register be as soon as the fourth bit is stored?
***5. Explain the main difference between the DIP and SMT packages.
Chapter- 2
Number Systems, Operations and Codes
* 6.
How many bits are required to represent nthe following decimal numbers?
(a) 17 (b) 35 (c) 49 (d) 68 (e) 81 (f) 114 (g) 132 (h) 205
* 7.
Conver each binary number to Gray code.
(a) 11011 (b) 1001010 (c) 1111011101110
* 8.
Convert each Gray code to binary.
(a) 1010 (b) 00010 (c) 11000010001
* 9.
Conver each excess -3 code number to decimal.
(a) 0011 (b) 1001 (c) 0111 (d) 01000110 (e) 01111100
* 10. Assume that the system is set up for 25 tablets per bottle. Determine the binary
numbers at each of the following locations in the system after 15 tablets have gone
intoi the 1000th.. bottle.
(a) In register A
(b) Input A to comparactor
(d) In register B
(e) Output of adder.
(c) In the counter
Chapter -3 (Logic Gates)
* 1.1. The input waveform shown in figure is applied to an inverter. Sketch the timing
diagram of the output waveform in proper relation to the input.
Vin
* 12. A network of cascaded inverter is shown in figure. If a high is applied to point A,
determine the logic levels at points B through F.
A
B
C
D
E
F
* 13. The input waveforms applied to a 3-input AND gate are as indicated in figure. Show
the output waveform in proper relation to the inputs with a timing diagram.
A
B
C
* 14. The input waveforms applied to a 4-input AND gate are as indicated in figure. Show
the output waveform in proper relation to the inputs with a timing diagram.
A
B
C
D
* 15. Determine the output waveform of NAND gate in figure.
A
B
C
D
* 16. Repeat problem 15 for a 4-input NOR gate.
* 17. The NAND and negative-OR symbols represent equivalent operations, but they are
functionally different. For the NOR symbol, look for at least one HIGH on the inputs
to give a LOW on the output. For the negative-AND ,look for two LOWs on the
inputs to give a HIGH output. Using these two functional points of view, show that
both gates in figure will produce the same output for the given inputs.
A
B
* 18. How does an exclusive-OR gate differ from an OR gate in the logical operations?
**19. In the comparison of certain logic devices, it is noted that the power dissipation for
one particular type increases as the frequency increases. Is the device TTL or CMOS?
* 20. Assume that the tablet counting and control system is set for 75 tablets per bottle.
Draw the timing diagram that you should see on the logic analyzer for the ten sensor
pulses up to and including the final count.
* 21. Sensors are used to monitor the pressure and the temperature of a chemical solution
stored in a vat. The circuitry for each sensor produces a High voltage when a specified
maximum value is exceed in alarm requiring a low voltage input must be activated
when either the pressure or temperature is excessive. Design a circuit for this
application?
***22. Design a circuit to fit in the colored block of figure that will cause the headlights of an
automobile to be turned off automatically 15 s after the ignition switch is turned off, if
the light switch is left on. Assume that a LOW is required to turn the lights off.
Ignition switch
Hig
High=on
Low= off
LOW turns
High=on
Low= off
Headlights
control
Off the lights.
Light switch
** 23. In the tablet counting and control system, the tablet feeder and conveyor mechanisms
have been changed to a different model. In the new model , the valve requires a LOW
level to close and the conveyor requires a LOW to a advance . Register B till requires
a HIGH level to store the new total count.
Modify the comparator logic to
accommodate this requirement.
Chapter-4
Boolean Algebra and Logic Simplification
* 24. Apply DeMorgran’s theorem to the following:
(a) (ABC)(EFG ) + (HLJ) (KLM)
(b) (A + BC ) + CD) + BC
(c) (A + B) (C + D) (E + F) (G + H)
***25. Draw the logic circuit represented by each expression:
(a) A B + A B (b) AB + A B + ABC (c) A B(C + D) (d) A + B [C + D(B + C )]
* 26. Using Boolean algebra techniques, simplify the following expressions as much as
possible.
(a) A (A +B)
(b)
A (A + AB)
(c)
BC + BC
(e) A BC + ABC + A BC (f) ABCD + AB (C D) + ( A B)CD
(g) ABC [ AB + C ( BC + AC )]
** 27. Convert the following expressions to SOP forms:
(d)
A (A + AB)
(a) (A + B)(C + B) (b) (A + BC)C (c) (A+C) (AB+AC)
** 28. Convert the each SOP expressions in problem 26 to POS forms.
* 29. Develop a truth table for each of the SOP expressions:
(a) AB + ABC + A C + ABC (b) X + Y Z + WZ + X Y Z
* 30. Develop a truth table for each of the POS expressions
(A+B)(A+C)(A+B+C) (b) (A + B)(A + B + C)(B + C + D)(A + B + C + D)
* 31. Use a Karnaugh map to simplify each expression to a minimize SOP form.
(a) A B C + A BC + ABC + ABC (b) AC [ B + B(B + C)] (c) DE F + DE F + D E F
(d) A + BC
* 32. Use a Karnaugh map to simplify each expression to a minimize POS form.
(a) (A + B + C + D)(A + B + C + D)(A + B + C + D)
(b) (X + Y)(W + Z)(X + Y + Z)(W + X + Y + Z)
***33. Minimize the following SOP expression using a Karnaugh map:
X = AB CDE + A B CDE + A B CDE + AB C D E + ABCD E + ABC DE + A B C D E
+ A BCDE + ABCDE + ABCDE
** 34. If you are required to choose a type of digital display for low light conditions, will
you select LED or LCD 7-segment display? Why?
* 35. Forsegment b, how many fewer gates and inverters does it take to implement the
minimum SOP expression than the standard SOP expression?
* 36. Redesign the logic for segment b through g using a minimum POS approach. Which
is simpler, minimum POS or the minimum SOP?
Chapter-5
Combinational Logic
** 37.Write the output expression for each circuit as it appears in figure.
A
A
A
X
X
B
B
X
B
(b)
(a)
A
(c)
A
A
B
X
B
B
X
X
C
(d)
C
(e)
(f)
* 38. Develop the truth table for each circuit in problem 36.
* 39. Show that an exclusive-NOR circuit produces a POS output.
* 40. Use NAND gates, OR gates, and inverters as needed to implement the following logic
expressions as stated:
(a) X = AB + BC (b) X = A(B + C) (c) X = A B + AB (d) X = A B C + B(EF + G )
(e) X = A[ BC ( A + B + C + D)] (f) X = B(CDE + EFG)(A B + C)
* 41. Implement a logic circuit for the truth table.
Inputs
Output
A
B
C
X
0
0
0
1
0
0
1
0
0
1
0
1
0
1
1
0
1
0
0
1
1
0
1
0
1
1
0
1
1
1
1
1
* 42. Simplify the circuit in figure as much as possible, and verify that the simplified circuit
is equivalent to the original by showing that the truth tables are identical.
A
X
B
C
* 43. Repeat problem 41 for the circuit in figure.
A
B
X
C
* 44. Implement the logic circuit in figure of problem 42 using only NAND gates.
* 45. Implement the logic circuit in figure of problem 42 using only NOR gates.
* 46. Show how the following expressions can be implemented as stated using only NAND
gates.
(a) X=ABC (b) X = ABC (c) X=A + B (d) X = A + B + C (e) X = AB + CD
(f) X=(A+B) (C+D) (g) X = AB[C(DE + AB) + BCE]
* 47. For the logic circuit in figure, sketch the output waveform in proper relationship to the
inputs.
A
A
B
X
B
** 48. For the inputs waveform in figure, what logic circuit will generate the output aveform
shown?
A
IN P U T
B
C
X
O U T PU T
** 49. Implement the lubrication motor logic in figure with NOR gates and inverters.
S1
S2
S3
S4
** 50. Develop the logic circuit necessary to meet the following requirements:
A lamp in a room is to be operated from two switches, one at the back door and one
at the front door. The lamp is to be on if the front switch is on and the back switch is
off, or if the front switch is off and the back switch is on. The lamp is to be off if both
switches are off or if both switches are on. Let a HIGH output represent the on
condition and a LOW output represent the off condition.
***51. Develop the NAND logic for a hexadecimal keypad encoder that will convert each
key closure to binary.
Chapter-6
Functions of Combinational Logic
** 52. The following sequences of bits (right most bit first) appear on the inputs to a
74LS83A adder. determine the resulting sequence of bits on each output.
A1
10010110
B1
11111000
A2
11101000
B2
11001100
A3
00001010
B3
10101010
A4
10111010
B4
00100100
***53. Each of the eight full adder in an 8-bit parallel ripple carry adder exhibits the
following propagation delays:
A to Σ and Cout
: 40 ns
B to Σ and Cout:
40 ns
Cin to Σ
: 35 ns
Cin to Cout
: 25 ns
Determine the maximum total time for the addition of two 8-bit numbers.
* 54. The waveforms in figure are applied to the comparators. Determine the output(A=B)
waveform.
COMP
A0
A0
A1
A1
B0
B0
B1
x1
*/*
x2
A=B
u1
x3
x4
B1
** 55. BCD numbers are applied sequentially to the BCD to decimal decoder. Draw a timing
diagram, showing each output in the proper relationship with the others and with the
imputs.
A0
A1
A2
A3
***56. Show the logic required to convert a 10-bit Gray code to binary and use that logic to
convert the following Gray code words to binary.
(a) 1010000000
(b) 0011001100
(c) 1111000111
(d) 0000000001
* 57. If the data select inputs to the multiplexer are sequenced in figure., determine the
output waveform with the data inputs :D0=0, D1=1, D2=1, D3= 0.
* 58. Develop the total timing diagram (inputs and outputs) for a 74154 used in a
demultiplexing application in which the inputs are as follows: The data-select inputs
are respectively sequenced through a straight binary count begining with 0000, and
the data input is a serial data stream carrying BCD data representing the decimal
number 2468. The least significant digit (8) is first in the sequence,with its LSB first,
and it should appear in the first 4-bit positions of the output.
WORKOUT EXAMPLES
1.
Digital can be transmitted and stored more efficiently and reliably.
2.
(i)
Period= 4 ms
(ii)
Frequency= 250 Hz
(iii)
Duty cycle= 50%
3.
Total serial transfer time = 8 µs
4.
Total parallel transfer time = 1 µs
5.
01010000
10.
(a) 00100101 (25 BCD)
(b) 00011001 (25 binary)
(c )00001111 (15)
(d) 0110000110010010 (24975)
(e) 0110000110100001 (24990)
13.
A
B
C
14.
A
B
C
D
Output
17. A
B
NOR output
Negative AND output
18. XOR = A B + AB .;
OR = A+B
19. CMOS
21.
Temperature sensor
NAND
gate
Alarm
Pressure sensor
22.
Ignition
Timer
Light switch
23. The valve and conveyor line must be taken from the NAND gate output. The register
lines still comes from inverter.
24.(a) (A + B + C)(E + F + G )(H + I + J )(K + L + M )
(b) A BC (C + D) + BC
(c ) A B C D E F G H
26.(a) A(A+B) = A+AB = A (1+B) = A
(b) A (A + AB) = AB
(c) BC + BC = C
(d) A (A + AB) = A
(e) A BC + ABC + A BC = BC + ABC
(f) ABCD + AB(C D) + ( A B)CD = CD ( AB + AB) + AB CD = CD + AB CD
= AB + CD
(g) ABC [ AB + C ( BC + AC )] = ABC
29.
(a) AB + ABC + A C + ABC (b) X + Y Z + WZ + X Y Z
A
B
C
X
0
0
0
1
0
0
1
0
0
1
0
1
0
1
1
1
1
0
0
0
1
0
1
1
1
1
0
1
1
1
1
0
W
X
Y
Z
Q
0
0
0
0
1
0
0
0
1
1
0
0
1
0
1
0
0
1
1
1
0
1
0
0
0
0
1
0
1
1
0
1
1
0
1
0
1
1
1
0
1
0
0
0
1
1
0
0
1
1
1
0
1
0
1
1
0
1
1
1
(b)
1
1
0
0
0
1
1
0
1
1
1
1
1
0
1
1
1
1
1
1
A
B
C
X
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
1
A
B
C
D
X
0
0
0
0
1
0
0
0
1
0
0
0
1
0
1
0
0
1
1
1
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
1
1
0
1
0
0
0
1
1
0
0
1
0
1
0
1
0
0
1
0
1
1
1
1
1
0
0
1
30.(a)
(b)
1
1
0
1
1
1
1
1
0
1
1
1
1
1
1
32.(a) CD
00
AB
01
11
10
00
(A + B + C + D)(A + B + C + D)(A + B + C + D)
0
01
0
11
0
10
.(b)
YZ
WX
00
00
01
11
10
0
0
0
0
0
0
01
11
0
0
10
Q = (W + X)(W + Z)(X + Y)
34.
LED, LEDs emit light. LCDs do not.
35.
One less inverter and six fewer gates.
36.
Segment b = (C + B + A) (C + B + A)
C
b
B
A
c = C+B+A
d= (D + C + B + A ) (C + B + A) (C + B + A)
e = A (C + B )
42.
f = ( D + C + A)(C + B )( B + A)
g = (D+C+B) ( C + B + A)
X = AB + ABC = AB (1+C) = AB
A
B
C
ABC
AB
ABC+AB
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
1
0
1
0
0
0
1
1
0
0
1
1
1
1
1
1
1
1
By truth table
AB+ABC = AB
46.(a) X=ABC
A
B
X
C
(c) X= A+B
A
A+B
B
(g) X = AB[C(DE + AB) + BCE]
A
B
D
E
B
E
C
C
A
B
X
47.
A
A
X
B
B
48.
A
X
B
C
49.
S1
S4
M
S2
S3
50.
A
B
X (Lamp)
51.
52.
Σ1 = 0110110
Σ2 = 10110100
Σ4 = 00010100
Σ5 = 10101010
53.
225 ns
54.
A=B is high when A0 = B0 and A1 = B1.
56.
(a) 1010000000 Gray
Σ3 = 01101000
(b) 0011001100 Gray
1100000000 Binary
0010001000 Binary
(c) 111100011 Gray
(d) 0000000001 Gray
1010000101 Binary
G9
B9
57.
G8
B8
G7
B7
G6
B6
0000000001 Binary
G5
B5
G4
B4
G3
G2
B3
G1
B2
G0
B1
B0
58.