1. No category

LOGIC
SYSTEM
AND DESIGN
LAB MANUAL (scan)
Computer (2010-2014) Branch
Third Semester
rilffF5
INSTRUCTION
IVIANUALS
FOR
IUODULES
OF
DIGITAL
I.AB
EXPERIMENTS
2245,OPP.DHULAHOUSEBAPUBAZAR,JAIPUR- 302OO3
E : (OFF.)2579523,2572194,(RES.)
ZST0EI}I
E,MAIL : sujatajprl @hotmail.com
INDEX
DecriPtionof Module
LogicGates
Gates- NAND/ NORGates
Universal
EX-ORGatelmPlimentation
EX-ORGateAPPlications
Theorem
Demorgan's
(Binaryto Gray& Grayto Binary)
CodeConversion
(Binaryto Excess- 3 Codes)
CodeConversion
BinaryAdder/Subtractor
Decoder(8 to 3 LineEncoder'3 to 8 LineDecoder)
Encoder/
Page No'
?
^
o
8
10
11
14
16
18
21
& 1:4LineDemultiplexer)
(4.1LineMultiplexei
Demultiplexer
Multiplexer/
FlipFlops(RS,D, JK & T TypeFlipFlops)
23
4-BitShiftRegister(Serialin ParallelOut)
BinaryCounter(UPCounter)
4-BitSynchronous
28
4-BitBinaryRippleCounter(UP/DOWNCounter)
31
Decoder
BCDto 7-Segement
(R-2RLadcjer
Network)
AnalogConverter
Digitalto
32
_lC'sPinConfigurations
36
25
30
v
PageNo. Z 39
INSTRUCTIONMANUAL
FOR
Logic Gates
of all Logic Gates'
OBJECTIVE: To study Operation
printed
provided with berow mentioned rc's with Logic Diagram
Modure
:
Description
Modure
brought out at 2mm sockets'
on the front panel & connections
ComPonents
2.
lC 74082 inPutANDGate'
lC743?2 inPutORGate'
3.
\C74OO2inPutNANDGate'
4.
5.
lC74O22inPutNOR Gate'
1C74862inPutEX-ORGate'
6.
1C7404NOTGate'
1.
QuantitY
1
1
1
I
1
4
I
4
PROCEDURE:
1.
of
Trainerto the supplyterminals
connect+5V DC supply& GNDpointfromthe DigitalLogic
module.
2.
SettheDigitalLogicTrainerinTTLmode'
ANDGate
4.
to Logicoutputsof DigitalLabTrainer'
ConnectAl& B1 inputterminals
LabTrainer.
sectionof Digital
Observe
thelogicouiputY1 on Logiclndicator
5.
VerifyTruthTableofANDGate.
3.
NANDGate
7.
to Logicoutputsof DigitalLabTrainer.
Connect
A4 & 84 inputterminals
sectionof DigitalLabTrainer.
Observe
thelogicoutputY4on LogicIndicator
8.
VerifyTruth
Tableof NANDGate.
6.
ORGate
10.
Connect42& 82 inputterminals
to Logicoutputsof DigitalLabTrainer.
ser,tionof DigitalLabTrainer.
Observe
thelogicoutputY2 on LogicIndicator
11.
VerifyTruthTableof ORGate.
9.
Page No. 3/ 39
" G.)
Y
" G
N A N DG A T E
AND GATE
OR GATE
5l., Y
NOT GATE
NORGATE
EX-OR GATE
OUTPUT
I N P U T1
INPUT2
o
A
B
o
0
0
0
0
1
0
1
0
0
1
1
I
0
0
1
0
1
1
1
1
1
1
0
INPUT1
INPUT2
OUTPUT
A
B
0
NANDGATE
AND GATE
OUTPUT
I N P U T1
INPUT2
o
A
B
o
0
U
0
't
v
0
1
1
0
1
0
1
0
1
1
0 '
0
1
1
1
1
1
0
INPUT1
I N P U T2
A
B
n
OUTPUT
NOR GATE
OR GATE
INPUT1
INPUT2
OUTPUT
A
B
o
0
0
0
0
1
1
1
0
1
1
1
0
INPUT
OUTPUT
0
1
1
0
NOT GATE
EX-ORGATE
P a g e N o4 / 3 9
*r'
i-lORGate
12.
13
14.
Logicoutputsof DigitalLab Trainer'
ConnectA5& 85 inputterminalsto
sectionof DigitalLab Trainer'
Observethe logicoutputY5 on Logiclndicator
-rableof NOR Gate'
V'erifyTruth
EX-ORGate
15.ConnectA3&83inputterminalstoLogicoutputsofDigitalLabTrainer.
of DigitalLab Trainer'
observe the logicoutputY3 on Logic lndicatorsection
16.
17.
VerifyTruthTableof EX-ORGate'
NOT Gate
19.
connectAo inputterminalto logic outputof DigitalLab Trainer.
Observethe logicoutputYOon LogicIndicatorsectionof DigitalLab Trainer'
20.
VerifYTruthTableof NOT Gate.
1g.
.f
Page No. 5/ 39
INSTRUCTIONMANUAL
FOR,
UniversatGates - NAND/ NOR Gates
the NAND & NOR Gatesas
OBJECTIVE: To study
UniversalGates'
rc's with Logic Diagram printed
: Modure provided with berow mentioned
Modure Description
brought out at 2mm sockets'
on the front panel & connections
TTL lC-741S00
Quad2-inputNANDGate
lC-74LS02
Quad2-inputNORGateTTL
Ti-reExPerimentlncludes
1.
2.
3.
4.
5.
6.
7.
8.
ANDgateUsingNANDGates'
ORGateUsingNANDGates'
NORGateUsingNANDGates.
NOTGateUsingNANDGates'
NANDGateUsingNORGates.
NOTGateUsingNORGates.
ORGateUsingNORGates.
ANDGateUsingNORGates.
Mddule Panel
.'l""
A5
I
B5
A5
86
Page No. 6/ 39
Truth Table:INPUT1
INPUT2
OUTPUT
INPUT1
INPUT2
OUTPUT
B
o
A
B
o
A
0
0
0
0
0
0
1
0
0
1
1
,l
0
0
1
0
1
1
1
1
1
1
1
0
NAND GATE
AND GATE
INPUT1
INPUT2
OUTPUT
o
A
B
o
0
0
0
0
1
0
1
1
0
I
0
1
0
1
1
0
0
1
1
1
1
1
0
INPUT1
INPUT2
A
B
0
OUTPUT
NOR GATE
OR GATE
INPUT
OUTPUT
PROGEDURE:
1
0
l.Connectthe+5r/DCsupp|y&GroundfromDigita|LabTrainerto
0
1
themodulePointsi,e+ 5V & GND.
NOT GATE
Setihe DigitalLabTrainerlnTTLmode.
2.
B1 & verifythe
the logicinputsfromthe DlgitalLabTrainerto themodulepointsA1 &
Connect
3.
truthtableof ANDGateoutputY1.
4.
3 for
Applytheprocedure
"
*
oR gateusingNANDGates;
*
ApplyinputsatA3 & 83 andobserveat Y3
NOR(ate usingNANDGates; Applyinputsat 42 & 82 andobserveat Y2.
NOTgateusingNANDGates; ApplyinputsatA4 & observeat Y4.
NANDgateusingNORGates; ApplyinputsatA5 & 85 andobserveat Y5.
*
NOTgateusingNORGates;
ApplyinputsatA7 & observeat Y7.
*
oR gtaeusingNoR Gates;
.
ANDgateusingNORGates;
ApplyinputsatA6 & 86 andobserveat Y6.
ApplyinputsatAS& BBandobserveat YB.
*
PageNo. 7/ 39
INSTRUCTIONMANUAL
FOR
EX-ORGate lmplementation
& EvenFarityGenerator.
Gatelmplementation
as ODDParityGenerator
: EX-OR
OBJECTTVE
printed
Module Description: Module Provided with below mentionedlc's with Logic Diagram
on the front panel & connectionsbrought out at 2mm sockets.
Quad2 InPutLX-ORGate
- 74LS86
Hex.lnverter
- 74LS04
Q u a d2 I n P u tO R G a t e
-74L532.
ModuleDesiqne
II
EX-ORGSTEI}lP tEI'IEHT6TIO
TruthTable:-
A
B
c
1
0
0
0
1
0
0
0
0
'1
1
0
0
0
1
0
1
0
1
I
1
0
1
1
1
1
0
0
0
1
0
0
1
A
t
0
1
1
1
1
1
1
1
0
1
1
0
,l
0
1
1
1
0
1
1
0
,l
A
B
c
0
0
0
0
0
0
OUTPUT
FOR ODD PARITYGENERATOR
OUTPUT
1
I
FOREVENPARITYGENERATOR
PageNo. 8/39
%""ttn"+5VDCsupp|y&GroundfromDigitaiLabTrainertothemodulepointsi,e+5V&
GND.
SettheDigiialLabTrainerinTTL mode
Z.
pointsA & B & c verifythetruthtable
inputsfromthemainmoduletothemodule
logic
the
connect
3.
OutPut'
of ODDParitYGenerator
4.App|yineSameprocedureforEvenParityGenerator&Verifyit'sTruthTable.
Page No. 9/ 39
INSTRUETION MANUAL
FOR
EX-OR Gate APP|ications
oBJEGTIVE:TostudyEXoRgateApp|icationasbinarywordComparator.
printed
Providedwith belowmentionedlC's with Logic Diagram
ModuleDescription: Module
broughtout at 2mmsockets'
on the front panel& connections
Quad2-lnPutEX-ORGate
- 74LS86
HexInverter
- 74LS04
Dual4-lnputNANDGate
- 74LS20
ModuleDesiqn
1.
Connectthe +5VDC supply& GroundfromDigitalLabTrainerto the modulepointsi,e+ 5V &
GND.
2.
SettheDigitalLabTrainerinTTLmode.
3.
Connect
thelogicinputsfromtheDigitalLabTrainerto themodulepointsA,B, C , D , E , F , G & H .
of I bit LEDDisplay'
Alsoconnectoutputlogicto oneof theterminal
lA
c
E
Firstword
Gl
|'
'l
lur-.oilo
outputis Lowi,e LEDglow'sGreen& whenFirst
WhenFirstWord= SecondWordthecomparator
O/Pis Highi.e.LEDglow'sRED.
wordnotequalSecondWordthecomprater
PageNo.10/39
M ANUAL
IN STRUCTION
FCR
Demorgan'sTheorenr
prove Demorgan'sTheorem
OBJECTIVE: To
lC's with Logic Diagram Printed
: Module Provided with below mentioned
Description
Modrrle
sockets"
& connections brought out at 2mm
on the front panel
I
2
Tripple3-lnPutAND Gate
Quad,3lnPutNOR Gate
Hexinverter
- 741511
-74L527
- 74LS04
ModuleDesign
LogicGircuitfor Demorgan'sTheorem- 1
A.B.C= A+B+G
$an
f,e
Z C
TI
OUTPUTLT
A+E+e
Tz
OUTPUT
P a g e N o .1 ' l i3 9
.
J
Truth Table:
0
0
0
'
0
0
0
1
0
0
1
1
1
1
1
1
1
'
l
o
1
0
1
1
1
0
0
0
0
0
1
1
1
0
1
0
1
0
1
1
0
0
0
1
1
1
1
0
0
0
ABC
A+B+C
0
1
1
0
\
I
0
1
1
0
1
1
0
1
I
0
1
1
0
'l
1
1
0
0
Theorem- 2
Logic Circuit for Demorgan's
A.B'C= A+B+C
'
g
F
f
L
)A
B
Tr
OUTPUT
4 c
A-E.E
TZ
OUTPUT
A+B+C
A.B+-G
-n.-e3'
A
B
C
A
B
0
0
0
1
1
,
0
1
1
0
0
1
1
1
0
1
O
0
0
1
0
1
0
1
O
0
0
1
1
1
0
0
1
,l
O
0
1
0
0
0
1
I
1
O
0
1
0
1
0
1
0
1
O
0
1
1
0
0
0
1
1
o
0
1
1
1
0
0
0
1
0
0
PageNo.12139
-J
PROCEDURE:
1.
pointsi'e + 5V &
from DigitalLab Trainerto the module
Connect tne +5V DC supply& Ground
GND.
SettheDigitalLabTrainerinTTLmode'
thelogicinputsatA5,85 & c5 andtheir
Theorem1 andconnect
MakethecircuitforDemorgan's
complimentstoA6'86&C6'RespectivelyfromsBitDataSwitchesofDigita|LabTrainer.T
sectionof DigitalLabTrainer'
on LEDDisplay
outputlogicis observed
Theorem1
VerifytheTruthTablefor Demorgan's
Theorem2 andconnectthelogic
to circuitfor Demorgan
according
Nowmaketheconnections
on
to A5, 85 & C5.Theoutputlogicis observed
inputsat 46, 86 &.C6.Alsotheircompliments
sectionof DigitalLabTrainer.
LEDDisplay
Theorem2'
VerifytheTruthTablefor Demorgan's
Page No. 13/ 39
INSTRUCTICNMANi.''AL
FOR
Code Conversion (Binary to Gray & Gray to Binary)
& Grayto Binarycodeconversion'
: TostudyBinaryto GrayCodeconversion
oBJECTIVE
ModureDescription:Modureprovidedwithberowmentionedrc'swithLogicDiagramprinted
connections brought out at 2mm sockets'
on the front panel &
2 Nos.
tC74862inPutEX-ORGate
ModuleDiagram:
p,ffiot
ISO9001:2000
cdlfad
m"
(oDE convERslgntBtltf,RYTg cR6Y s cRflYTo BlltgRY)
NAFS
DE-06
cdFny
{MSB)
{MSBI
(MsB)
G 3 -
8 0 1
_l
GRAY TO BINARY
BINARYTO GRAY
TruthTable:
0
0
0
1
0
1
1
0
0
1
0
0
0
1
1
0
0
1
0
1
1
1
1
1
0
0
1
0
1
0
1
1
1
0
1
0
0
1
0
0
0
1
i
o
0
1
0
0
1
1
1
0
1
1
0
1
1
1
1
1
1
0
1
1
1
0
1
1
0
1
,l
0
1
0
1
1
0
1
0
1
1
1
1
1
0
0
1
1
1
1
,l
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
1
1
0
0
,l
0
0
1
0
,
BINARYTO GREY CODE CONVERSION
P a g eN o . 1 4 1 3 9
Connect the
+5V D C s u p p l y & G r o u n d f r o m D i g i t a | L a b T r a i n e r t o t h e m o d u | e p o i n t s i ' e + 5 V &
GND.
Setthe DigitalLabTrainerin TTL mode
:
BCD to GraYGode
of DigitalLabTrainerto the modulepointsA' B' C
?
Connectthe logicinputsfromthe Logicoutputs
to the terminalsof B bit LED Displaysectionof
& D. AlsoconnectoutputlogicsQo,Q", Q" & Qo
DigitalLabTrainer.
Verifythe TruthTable.
Grayto BGD Code :
3.
the modulepointsG0,G1,
Connectthe logicinputsfromthe Logicoutputsof DigitalLabTrainerto
Displaysection
G2 & G3.Atsoconnectoutputlogics80, 81,B;2&83 to the terminalsof B bit LED
of DigitalLabTrainer.
4.
VerifYthe TruthTable.
82
B1
BO
0.
0
0
0
1
0
0
0
1
0
0
0
1
1
,l
0
1
1
0
0
1
0
0
1
0
0
0
1
1
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
0
0
0
1
1
1
0
1
0
1
1
0
0
0
1
1
1
1
1
0
0
1
1
1
1
0
1
0
1
0
1
1
0
0
1
0
1
1
1
1
0
1
1
1
0'
0
1
0
0
0
1
A
I
0
1
t
0
0
1
1
1
1
0
1
0
1
1
1
1
1
1
1
0
1
0
G3
G2
' 0
G1
GO
0'
0
0
0
0
0
0
0
0
83
GREYTO BINARYCODECONVERSION
Page No. 15/ 39
J
INSTRUCTIONMANUAL
FOR
Code Gonversion (Binary to Excess-3Codes)
: TostudyBinaryto Excess-3CodeConversion'
OBJECTIVE
mentioned lC's with Logic Diagram printed
Module Description : Module Provided with below
on the front panel & connections brought out at 2mm sockets.
Quantity
GomPonents
I
2.
lr}74322inPutORGate.
Gate
lC74082 inPutAND
3.
tC7404NotGate
1
1.
1
coDEcotwERsloll
(ODESI
{ BCDTOEXCESS-3
Module Diagram:
TruthTable:
EKI
82
B1
BO
H}
E2
E1
0
0
0
0
0
0
0
0
-1
I
0
0
,l
EO
'l
0
0
0
0
1
0
0
,l
0
1
0
0
1
1
0
1
1
0
0
1
0
0
0
1
1
1
0
1
'1
0
1
1
0
0
0
1
0
1
0
0
I
0
1
1
1
I
0
1
0
1
0
0
0
1
0
1
1
1
0
0
1
1
. 1
0
0 r
1
0
1
0
1
1
0
1
1
0
1
1
I
1 ' , 1
0
1
1
0
0
1
1
1
0
1
Page No. 16/ 39
PROCEDURE:
+
&
from DigitalLab Trainer to the rnodulepoints i'e 5V
.r
connect ihe +5V DC supply& Ground
GND.
SettheDigitalLabTrainerin TTL mode'
of DigitalLab Trainerto the modulepointsB0' 81 '
connectthe logicinputsfrom the Logicoutputs
E|, E2& E3 t'othe terminalsof B bit LED Displaysection
82 & 83. Also connectoutputlogicsE0,
of DigitalLabTrainer'
VerifytheTruthTable'
PageNo.17139
INSTRUCTiONMANUAL
FOR
Bi narYAdder/ Subtractor
o B J EGT |V E :T o stu d yB i n a ryAdder /Subtr actor using|C7483.
panel& connections
: Module Providedwith Logic Diagramprinted on the front
ModuleDescription
brought out at 2mm sockets'
of lnputs & Outputs
THEORY:
areusedhere'For
binaryadder& subtractors
Parallel
or Subtraction,
For4 bitnumbersAddition
Thetwonumbersbeingaddedare43,
in parallel.
we need4 fulladderconnected
Two4 bitnumbers
adding
carryif the
overflow
BO& thesum is s4, s3, s2, sl, s0. where s4 indicates
M, A1,A0 & 83, FJ2,F,1,
sumexceedsfrombits'
we can directlysubtract4 bit
teo 4 bit numbers,we needfour Fullsubtractors.
Forsubtracting
4 bit numbersi.e.We cansubtract83 82 81 B0 fromA3'A2' A1'A0'
i.e.We cansubtract
numbers
ModuleDiagram:
BfnsRYADogRI SOBTRd(TOB
"*l
E>
h
tY
[D
St
Sz
St
S!
,,
.'S"'3
ere*k
.3,30{rk
.3ee*k
(tsB)
=
OUTPU'
INDICATOR
PageNo.18/39
.
J
Logic Gircuit for 4 Bit Adder :
OUTPUT INDICATOR
LoGIG'0'
13
lc 7483
8
1
0
'
{
6
4
7
'
'
1
Bz ler lBo
A3 lA2 lA{
SECONDWORDINPUT
FIRST WORD INPUT
Logic Circuit for 4 Bit Subtractor :
OUTPUT INDICATOR
{
5
2
6
9
lG 7483
13
8 1 0 1 6
FIRST I'YORDINPUT
SECOND YIIORDINPUT
PROCEDURE:
1.
modulepointsi,e + 5v &
the +5VDC supply& GroundfromDigitalLabTrainerto the
Connect
GND.
2.
3.
SettheDigitalLabTrainerinTTLmode'
fromDigital
i.e.connect4 Logicoutputs
4 BitAdciition
thecircuitas showin LogicCircuit
Connect
LogicTrainerto theinputsof lC 7483,FirstWordlnput'
4.
5.
o.
Connectother4LogicinputstotheBinputs(SecondWord)oflC7483'
inputthroughpatchcoard'
ConnecttheLogic'0'to CARRY(CrN)
outputat output
Addition
thecorresponding
ApplyBineryi/p'sat First& secondword& observe
indicators.
PageNo.
'19/39
For ExamPle:Add
0
1
1
0
&
AO
A 3 p a A 1
0
I
0
I
5
1
0
1
1
11
1
0
83
82
1
1
B1
BO
ii)
1
0
1
1
11
0
1
1
1
I
18
I
15
,
For 4 Bit Subtractor:
Note: Alwaysapplyhighernumberinputat"A',inputascompareto"B'input'lfword"B"ismorepositive
'A" in thatcasethiscircuitwillshowwronganswers'
as comparedto word
7.
Coonect4 logicinputsto the
to LcgiccircuitFor4-Bitsubtractorconnectthe circuitaccording
"A"inputsof lC 7483.
in Figure'
connectother4logicinputsto the"B"wordof lc 7483as shown
ApplyLogic'1'to carry(ClN)i.e'+5VDCthroughpatchcoard'
in
remains
cutputi.e,1111if subtraction
showmaximum15numbers
Thissubtractorcircuitcan
positiveas comparedto B inputs'ignorecont'indicator'
plu.spositioni.e..inputsAwillremains
8.
9.
10.
For ExamPle:Subtractor
A 3 p a A 1
1
BO
AO
83
82
81
I
0
0
q
0
ip
1
0
0
0
I
0
1
0
0
4
1
1
1
1
1
1
15
0
0
0
0
0
15
PageNo.20/39
INSTRUCTIONMANUAL
FOR
Encoder/ Decoder (8 to 3 Line Encoder & 3 to 8 Line Decoder)
OBJECTIVE: To study Encoder / Decoder (8 to 3 Line Encoder,3 to 8 Line Decocier)
Module Description: Module Providedwith below mentioned lc's with Logic Diagramprinted
on the front panel & connections brought out at 2mm sockets.
Component
Quantity
1.
lC 7415322 inputORGate
2.
lC 741511
3 inputAND
Gate
3.
lC 74LS04HexInverter
3
1
Logic Diagram:
EilCODER/DECODER
{8 TO3 UttE E|(ODER"3TOE UNEDECODER
I
AND
t-l
BO
o1
lF
t-
v
ANO
GATE
D1
ANO
GATE
m
B1
D3
AND
04
I
-
AND
GATE
{)3
+rL_+
r
ANO
F
D€
DO
r
m
8 TO 3 LINEENCODER
D5
AND
E
tr
D6
AND
GATE
D7
3 TO 8 LINE DECODER
TruthTablefor 8 to 3 Line{Encoder):
DO
D1
D2
D3
Dt
D
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
5
D
6
D
7
X
Y
Z
0
0
0
,0
0
0
1
0
0
0
1
0
0
0
0
0
1
1
1
0
0
0
1
0
0
0
0
1
0
0
1
0
1
0
0
0
0
1
0
1
1
0
0
0
0
0
0
1
1
1
1
PageNo.21l39
(Decoder):
Truth Tablefor 3 to I Line
BZ
Bl
B0
Do
D1
D2
D3
D'l
Ds
D6
D7
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
1
0
1
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
1
0
1
1
1
0
0
0
0
0
0
0
1
NOTE: FourInputORGateis designedusingthree2 inputORGates.
1,
the+5VDC supply& Grounci
Connect
fromDigitalLabTrainerto themodulepointsi,e+ 5r,/&
GND.
2.
SettheDigital
LabTrainerinTTLmode.
8 to 3 Encoder:
Connect
thelogicinputsfromtheLogicoutputsof DigitalLabTrainerto thernodulepointsD0,D1
,
D2,'D3,
D4,D5,DO& D7.Also.Connect
outputlogicsX, Y & Z io theterminalsof
8 bitLEDDisplay
sectionof DigitalLabTrainer.
VerifytheTruthTablefor g to 3 Encoder.
to 8 Decoder:
connecttheiogicinputsfromtheLogicoutputs
of DigitalLabTrainertothemodulepoints80,B1
& 82'AlsoconnectoutputlogicsD0, D1,D2,
D3,D4,D5,D6 & D7 to theterminals
of g bitLED
Display
sectionof DigitalLabTrainer.
VerifytheTruthTable3 to g Decoder.
PageNo. 22l 39
___-J
IN STRUCTION
M ANUAL
FOR
(4:1LineMultiplexer& 1:4 Line Demultiplexer)
Demultiplexer
Multiplexer/
-1
OB;ECTIVE: To study Multiplexer/ Demultiplexer(4 Line Mux, 14 Line Demux.)
ModuleDescription: Module Providedwith below mentioned lc's with Logic Diagramprinted
on the front panel & connections brought out at 2mm sockets'
Quantity
1.
ComPonent
(4:1LineMultiplexer)
lC7415153
2.
(1:4LineDemultiplexer)
tC741S155
I
t
1
Multiplexer
meansmanyintoonei.emultiplexer
hasmanyinputsbutsingle
is a logiccircuitwhich
.l: . ,, Multiplexer
acceptsseveraldatainputsbutallowonlyaneof themat a timeto getthroughto the
A muitiplexer
output.
output.
l-ogicGircuitfor 4:1 Multiplexer:
Ao
6 I C
Bo
u
74
Co
4 .
1
DO
s
t
f,
3
't4
2
OUTPUT
INPUT
Sr. No STROBESELECTINPUT
GO
S1
s0
YO
1
0
0
0
AO
2
0
0
1
BO
3
0
1
0
c0
4
0
1
1
DO
Toperform4 to 1 linemultiplexer
experiment,
We haveusedlC 741sg.lthas4 Lineinputs(A0;80,
D0)& onlyoneoutputYOG0 is
the Strobeinput(Activelow)Sl, & S0 areselectlines.thesetines
oneoutof frominputsat outputfore.g.ifwewillapply
00 at 51 & S0 firstinput41 willbeselected
Page No. 23l 39
. __J
DemultiPlexer
performthe reverseoperationof multiplexer.
lt acceptsa singleinput& distributers
Thedemultiplexer
it overseveraloutPuts'
Logic Gircuitfor 1:4 Demultiplexer:
16
DATA
INPUT
1
STROBE
2
' I C
3
SELECT ST
iNPUT
I
,
I
6
4
1
)
_
OUTPUT
DICATORS
5
f,
So
Truth Table For 'l:4 Demultiplexer:
INPUT
OUTPUT
Sr. No STROBE SELECTINPUT
Ga
s1
SO
Y
1
0
0
0
YO
2
0
0
1
Y1
3
u
0
Y2
4
0
1
,,
1
Y3
Connect
the+5VDCsupply& GroundfromDigitalLabTrainerto themodulepointsi,e.+
5V &
GND.
SettheDigitalLabTrainerinTTLmode.
to 1 LineMultiplexer:
Connect
thelogicinputsfromtheLogicoutputs
of Digital
LabTrainerto theInputpointsof Multiplexer
circuitusinglc 74LS153 & outputat terminal
of 8 bitLEDDispray
sectionof DigitalLabrrainer.
VerifytheTruthTablefor4 to 1 Multiplexer.
to 4 LineDemultiplexer
:
Applylogic'1' (+sv DC)at inputterminal
of Demultiptexer
y0, y1, y2
& connectoutputterminals
& Y3 to B bit LEDDisplaysection
of Digitall_abTrainei.
VerifytheTruthTablefor 1 to 4
Demultiplexer.
: Hereyourealise
fromTruthTablethattheoutputis LogicLowat theselected
channel
& theother
showLogicHighthisis dueto
thefactthattheoutputtreminalactsas inverter
of inputdata.
PageNo. 24l 39
-.---]'--],...'F
INSTRUCTIONMANUAL
FOR
F l i p F l ops ( RS,D, JK, T Flip Flops)
: TostudyFlip- Flops{R-S,D,J-K& T TypeFlipFlops)
OBJECTIVE
: ModuleProvidedwith belowmentionedlG's with LogicDiagramprinted
ModuleDescription
on the front panel& connectionsbroughtout at 2mmsockets.
1.
,2.
lC741576(DualJKFliPFloP)
lC741500(Quad2 InputNANDGate)
3.
'4'.
lC741510(Dual3InputNANDGate)
lc74LS74(DualDFlipFlop)
:Module
Design
JK FLIP FLOP
L
H
H I L
L
L
H
L
L I H
H
H
L
t-
H I H
L
H
H
H
o ,l q
H
L
H
H
H l r -
H
H
H
H
L
H
H
a,
H
tobe used
I
H
P a g eN 0 . 2 5 l 3 9
JKFlinF
T Flip Flop
OUTPUT
INPUT
PRESET CLEAR CLOCK
X
H
L
o
INPUT
X
L
T
1
J
K
X
a
H
L
X
X
X
H
L
L
X
X
X
H
H
H
-rL
L
L
q
q
H
H
_J1_
H
L
H
L
H
H
_rL
L
H
L
H
H
JL
H
H
TOGGLE
OUTPUT
o
E-
Toggle
I H
I
PROGEDURE:
1.
Connectthe +5V DC supply& Groundfrom DigitalLab Trainerto the modulepointsi,e. + 5V &
GND.
2.
setthe DigitalLabTrainerin TTL mode.
R-SFlip Flop:
theR,S, PR.,CLRterminals
Connect
to theLogicoutputsof DigitalLabTrainerandClockterminal
to PulserSwitch(ActiveHigh)of DigitalLogicTrainer.
ConnectO & O terminals
(B Bit LED DisplaySectionof DigitalLogic
to the outputindicators
Trainer).
VerifytheTruthTablefor RS FlipFtops.
F l i pF l o p :
Connectthe J, K, PR & CLRterminals
to the Logicoutputsof DigitalLabTrainerand Clock
terminal
to PulserSwitch(ActiveHigh)of Digital
LogicTrainer.
ConnectO & a terminals
(8 Bit LED DisplaySectionof DigitalLogic
to the outputindicators
Trainer).
VerifytheTruthTablefor JK FlipFlops.
TypeFtipFtop:
Connect
theD, PR& CLRterminals
to theLogicoutputs
of DigitalLabTrainerandClockterminal
to PulserSwitch(ActiveHigh)of DigitalLogicTrainer.
ConnectO & E- terminals
to the outputindicators
(B Bit LED DisplaySectionof DigitatLogic
Trainer).
VerifytheTruthTablefor D FlipFlops.
PageNo.26/39
FloP:
"T'TypeFtiP
logicHighinputat
fortoggleFtipFlopbyapptyPulseat Clockterminaland
connection
12. Nowmake
PR& CLRterminals'
o & o terminalsto the outputindicators(B Bit LED DisplaySectionof DigitalLogic
ConnecJ
13.
Trainer)'
VerifltheTruthTablefcrT FlipFlops'
14.
given to the JK terminals'
NOTE:Logic'f is internally
,9.iii=,i.i1i":
PageNo.27l39
,
,-
--J
INSTRUCTIONMANUAL
FOR
4-Bit Shift Register(serial in ParallelOut)
study 4-Bit shift Register(serialin Parallelout using lc 74LS95)
oBJECTIVE: To
fi
: ModuleProvidedwith Logic Diagramprintedon the front panel& connections
*oou," Description
broughtout at 2mmsockets'
ModuleDesign
SHIFTRESISTORS
(MSB)
,,
3m
c
B
Oa
3m
t
. 7€5
c
o
la
{LsB)
i
I
A SHIFTregister
is basicaliy
a storagemediumwhereoneor morebinarywordsmaybe stored.
a counter,it is alsomadeup of binarystorageelements,
Theseelementsare
usuallyflip-flops.
in sucha waythatthe bit storedtherecanbe movedor shiftedfromoneelementto another
element.
by a singleinput'CLOCK'or
Allof thestorageregisters
simultaneously
areactivated
IFT'pulse.Whena shiftpuiseis applied,thedatastoredin theshiftregisteris movedoneposition
to leftor to rightas desired.
PageNo.28/39
Logic Circuit:
OUTPUTINDIGATORS
Qs
9QA
a
"
Qc
eo
14
rc 7495
I
A
LOGICINPUTS 7
B
c
D
S E R I E LI N P U T
PROCEDURE:
1'
Connect
the+5y DC suppiy& GroundfromDigitalLabTrainerto the modulepointsi,e.+ 5V
&
GND.
2.
SettheDigitalLabTrainerinTTLmode.
Connect
thecircuitas shownin LogicCircuitusingpatchcords.
J.
4.
connectclockinputto pulserswitch(ActiveHIGH)of DigitalLogicTrainer.
5.
Connect
theterminals
D,MODE& Seriallnputto Logicoutputs
fromDigitalLabTrainer,
putSerial
'1..
inputat Logic
6.
Putthemodecontrolswitchto logic'0'to enablethelC performRightShiftoperation.
put D input
to Ground(Logic'0').
7.
PutserialInputto logichigh(+5VDC).Apply4 clockpulsesfrompulserswitch
onebv oneand
8.
9.
10.
recordthefinaloutputlevelsi,e.eA eB eC eD = 11j1.
Setserialinputto ground.
Apply4 clockpulsesonebyoneandnotedownthedirection
in which
theDATAshift
(OutputDatashiftin RightDirection).
Putmodecontrolswitchto Logic'1'toenablethelC performLeft
Shiftoperation.
AlsoputtheD
inputto Logic'1'.Apply4 clockpulsesoneby oneandrecordthefinal
outputlevel
i , e .Q A Q BQ CQ D = 1 1 1 1
SetD inputto Logic'0'i,e.GND.Apply4 clockpulsesonebyone
otedownthedirection
inwhich
theDATAshift(OutputDatashiftin LeftDirection).
Page No. 29l 39
INSTRUCTIONli'iANUAL
FOR
4-Bit Synchronous Binary Counter (UP Counter)
OBJECTIVE: To study 4-BitSynchronousBinaryCounter(UPCounter)using lG 74LS163.
ModuleDescripticn: Module Providedwith Logic Diagramprintedon the front panel& connections
broughtout at 2mm sockets.
ModuleDesign
4 BtT SYNCHROTTOUS
Bttt6RY COUNTER
(0P cooltTER)
L
CK
OD
ENI
Oc
ENP
QB
?41 63
CR
G
lC 74LS163is an Synchronous
4-BitBinaryUP Counter.In this lC theirare two separateenable
Ripplecany
inputs,ENT& ENP.Settingeitherof theseinputsto Logic'0'stopscountingasynchronously.
(RC)output
goestotogic'1'whenever
isnonnally
atLogic'0'and
QD
oc
QB
OA
inhibits
RCchanging
fromLogic'0'toLogic'1'.Bychanging
0
0
0
0
Logicinputsat PAPB PC PDwe canalsodecidethehighest
0
0
0
1
outputcount.
0
0
1
0
0
0
1
1
0
1
0
0
Connectthe +5V DC supply& GroundfromDigital
0
1
0
1
LabTrainerto themodulepointsi,e.+ 5V & GND.
0
1
1
0
2.
SettheDigitalLabTrainerinTTLmode.
0
1
1
1
3.
A p p l yL o g i c ' 1 ' ( * 5 D
V C ) t oE N T E N P& C L R .
1
0
0
4.
NowStartsapplying
clockpulsesthroughpulserswitch
1
0
0
0
,l
(ActiveHigh)of DigitalLabTrainer.
1
0
1
0
WeobservethattheLogicIndicators
startsglowingin
1
0
1
1
1
1
0
0
thecounterreachesits highestcount.ENTto Logic'0'also
PROGEDURE:
1.
5.
, thefollowing
pattern
as showninTable.
o,
VerifytheTruthtable.
1
1
0
1
7.
Connect
ABCDterminal
to thelogicOutputterminals
1
1
1
0
of DigitalLogicTrainer.
1
1
1
J
PageNo.30/39
rl
. l
IT.ISTRUCTI
ON IV1ANUAL
FOR
4-BitBinaryRippteCounter(Up/DOWNCounter)
OBJECTIVE: Tostudy4-BitBinaryRipplecounter(Up/DowNcounter)usinglc
74LS193.
ModuleDescription: Module Providedwith Logic Diagramprinted
on the front panel& connections
brought out at 2mm sockets.
ModuleDesign
4 BrT BrItf,Ry RrppLEcguNrER (qp Dowlr cooHTERl
(MsB)
Oo
UP
CLOCK
INPU'
DN
QB
eree le
O^
.qe+ ^!a
CLEAR
CR
(,
7413
{LsB}
PUSIJTO
lc 74LS193is a synchronous
4-BituP/ DowN Binarycounter.In thislc, for up countingthe
clockis appliedat countUPterminaland
countDowN is connected
to Logic,1,.ForDowN counting
clockis appliedat counfDowN terminarwith
count-Upconnected
to Logic,1,.
PROCEDURE:
1'
connectthe+5y DC supply& GroundfromDigital
Labrrainerto the modulepointsi,e.+ 5y g
GND.
2.
SettheDigitatLabTrainerinTTLmode.
FORUP-COUNTER:
3.
ConnectCount-UpterminaltoactiveHighpulser
terminalLogic,1,(+SVDC)to Count_DOWN
terminal
andapplyclockpulseslhrough
pulserswitch.
4'
Theoutputindicators
growin theincreasing
,.
pattern
from,0000,
to ,1111
FORDOWN4OUNTER:
5'
Connectcount-DowNterminal
to ActiveHighpulserterminalLogic,1,to cK-Up
terminal
and
applyClockpulsesthroughpulserswitch.
6.
Theoutputindicators
growin thedecreasing
,0000,.
patternfrom,1111,to
PageNo.3tl39
INSTRUCTIONMANUAL
FOR
BCD to 7-SegementDecoder
OBJECTIVE: To study Conversionof BCDWord to 7-SegementDisplay(Decimal)using lG 74L547.
ModuleDescription: Module Providedwith Logic Diagramprintedon the front panel& connections
brought out at 2mm sockets.
-
ModuleDesign
t
BCDTO 7 SEGI,IETIT
DECODER
7 SEGMENT
DISPLAY
I
A digital
oitpr.vtn"t.it"ritt
"i
t a=oa*me
; *rron"u, usedtodisptay
decimat
numericals
indigitalsystem.
Forusingthedisplaydevicethedatahasto beconverted
fromsamebinarvcodeto the
coderequired
for thedisplay.
TruthTabte:
D
c
B
A
0
0
0
0
0
0
0
0
1
1
0
0
1
0
2
0
0
1
1
3
0
1
0
0
4
0
1
0
1
5
0
1
1
0
6
0
1
1
1
7
1
0
0
0
8
1
0
0
1
I
il
OUTPUT
PageNo 32l39
PROCEDURE:
1'
connectthe +5y DC supply& Groundfrom Digitai
Lab rrainerto the
^r rn
L)I\ LJ.
moduleporntsr,e + 5v &
2.
Setthe DigitalLabTrainerin TTL mooe.
3'
connectAB c D inputterminalsto Logicoutputsfrom
B-Bitdataswitchesof DigitalLabrrainer.
Nowverifythe truthtablefor BCDto Z_Segement
Decoder
4
PageNo 33/39
INSTRUCTIONMANUAL
FOR
Digital to Analog Converter (R-2R Network)
oBJEcrlvE: TostudyDigitat
to AnalogconverterusingR-2RLadderNetwork.
ModuleDescription: Module Providedwith Logic Diagramprintedon the
front panel& connections
brought out at 2mm sockets.
ModuleDesign
+t2v Dc
-1?\t Oc
R=1K2R-2K,3R=3K
Formulato R-2RLadderNetwork
Vor, =
-(RJ 3R). (V Z4l
RI [gb. + 4br+ 26r+ l bol
Whereb3,b2,b1,b0arelogic'sat terminals
D, C, B,A respectivety.
NOTE: We haveadjustedthe term -(R/ 3R) (VJ
.
DCas a stepssize.
Zol=0.5VDG.So that the modutework with 0.5V
PageNo.34/39
f
INPUT
OUTPUT
MSB
LSB
VOLTAGE
D
(inDCVotts)
A
B
c
0
0
0
-0.00
0
0
0
-0.50
0
0
1
-1.00
0
0
-1.50
0
1
-2.00
0
1
-2.50
I
0
1
0
1
1
,l
1
0
0
0
1
0
0
I
1
0
1
0
1
-5.50
I
'l
0
.6.00
0
1
1
€.50
-7.00
I
1
-7.50
l 0
,
1
.0
-3.00
€.50
4.00
-4.50
-5.00
PROGEDURE:
1'
connectthe+12y & -12vDc & GNDterminals
fromDigitalLabrrainerto the modulepointsi,e.
+12V& _12VDC & cND.
2.
SettheDigitalLabTrainerin TTLmode.
ConnectAB c D terminalto the Logicoutput
terminalsof DigitalLogicTrainer.
..
connecta digitalMultimeter
in20 VDCrangeacrosstheAnatog
Voltageoutputterminals
X &y
Nowverifythe,truth
table.
3'
4'
5.
Page No. 35/39
a
tp
13
14
VGG I
'
t
2
12
ll
3
4
lo
9
5
6
Pin Descriptionof lC 7400
.1!-.5
2-.3
-7
6
Pin Deseriptlonof !C 74A2
l
a
t
S
n
Ycc
Pin Descriptionof lC 7408
2.INPUTOR GATE
HEX INVERTER
Pin Description
f
2
l
L
5
6
7
PinDescription
oTlC Z+tl
3-INPUTAND GATE
PageNo.36/39
'
2
3
4
5
6
7
Pin Descriptionof iC Z42O
i
?
3
4
5
6
7
Pin Descriptionof lC T4B2
0ulpl1s
l
9
e
b
c
d
.
r 5 t l 1 3 r z f l t o . !
Vcc CLR 2Q 2CK 2pR 2e 2Q
1 4 1 3 1 2 1 1 1 0 9I
1
2
3
4
5
6
7
I C L R 1 Q 1 C K1 P R 1 Q 1 0 G N D
1
2
8
C
'
tngulr
tT B/hm nsl
6
7
D'. A
lnputr
Pin Descriptionof lG 7474
Pin Description of lC 7447
1 K 1 Q 1 Q G N D 2 K 2Q 2Q 2J
1 6 1 s 1 4 1 3 1 2 '11 10 g
8r
t
Sr Cor Ci
q t{rtl
n
E o A o $
n t r g
I
I
{
II
^, '; i i ', i i i
Pin Descriptionrf lC Z4g3
1
2
3
4
5
6
7
8
1CI(IPR1CLR1J VCC2CKzPR2CLR
'
Pin Descriptionof lC T4i6
PageNo.37l39
OutFrtr
O(
l4
r
l
(
,
55
6s
SE^LECI
r
t5
t|n
1
ln
2
3
tn,6
t3
t2
tc3 rcz tct
4r,self;n
-.!1L1
2v
to
5
s
7
e
tco tv
tnput: -Putput
-
Pin Descriptionof lC 74153
__Otd1l1rtr_
E
t
lher
rr'{,
-OulPuts
A
C2 GZ
Oata Slrobr SEtEf 2tB 2Y2 2Yl ?Y0
1 5 1 1 1 3 1 2 1 1 t 0 9
6utPu1
zcz zct zco
5
1
2
3
4
Detr StrobcSELECI
lY3
Cl
_
Gt A
(
3
5
PA PE pc
---&h
l|Pstl-
Pin Descriptionof lC 74163 .
5
7
lYt
tYO
8
O u t p u t s_
-Ine|rtr
triprrlr
on$ulr
P^ Cr 80ncr Crfrt tqd
t
b
'fz
t0
tt
ll
I
f5
t4
EtLDL
6
7 r 0
po Eneblc
P _.
5
lYz
Pin Descriptionof lC 74155
R C O r O . O c q t L d
l 5 t a B n n | 0 t
?
CX
Cont.
Pin Descriptionof iC 7495
Ddr Inputs-
a
t-----J
Itputt
*r
ll
Cl(l
O3 Oq Oo Rs ls(Lordt
e
I
tz.tr
E
1
2
t
1
5
6
7
* r - A B C O t l o d .
Pin Descriptionof lC 7486
?G @^
q^
R
I
rb
lnpul
2
O6
t
q
a
s
6
?
{
Ceud Cosot Oc
Oo,
Ooqn Up
Oulgutr -I||)uittOutputr
Pin Descriptionof lC 74193
Page No. 38/ 39
F
UJJ
o J
rLf
F
f
r
(O r F=
=
-
Bz
+
+
7
6
tc 741
2
F
l,rl
o
L
J
J
:)
o z
lr
3
(,
o
o
I
z
F
F f
E o.
||t 2
(l
z
F
T,F
ul 3
>o.
z z
z
o
z
Pin Descriptionof lC 741
PageNo. 39/ 39