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MIT International Journal of Electronics and Communication Engineering, Vol. 4, No. 2, August 2014, pp. 65–69
ISSN 2230- 7672 © MIT Publications
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Design Development and
Implementation of SPI
A. Sirisha
Dept. of ECE
SREC, Nandyal
Kurnool (DT), A.P, INDIA
M. Sravanthi
Dept. of ECE
SREC, Nandyal
Kurnool (DT), A.P. INDIA
N. Sreenivasa Rao
Dept. of ECE
SREC, Nandyal
Kurnool (DT), A.P. INDIA
ABSTRACT
There are many communication protocols for both short and long distance communication purpose such as ETHERNET, USB,
SATA, PCI-EXPRESS are used for long distance and I2C and SPI are used for short distance communications. SPI is a serial
interface protocol, compared to other protocols, it has high transmission speed, simple to use and little pins advantages. The
four interfaces are required by standard SPI protocol at least. Usually, the devices which based on SPI protocol are divided
into master device and slave-device for transmitting the data. The chip select signal and clock signal have be generated by
the master-device when the data exchange has been processed. SPI is often considered as the “little” communication protocol
which is used for ON-Board communication.
Although the literature on SPI protocol is so extensive and the topic is so old (early 1980), to the best of the authors knowledge
there is no comprehensive analysis of SPI problem. By comprehensive analysis, we mean a treatment that start from Motorola’s
V03.06 SPI bus specifications and goes down to the actual ASIC/FPGA implementation, discussing all relevant architectural
aspects and providing all design details. In our attempt to implement universal SPI IP cores according to the design- reuse
methodology, we first made a market study of an important number of recent commercial SPI devices (datasheets) from different
vendors to look at the requirements and what features are to be included to satisfy modern ASIC/SoC applications.
1. INTRODUCTION: SPI
Clock Line (SCLK)
The Serial Peripheral Interface (SPI) protocol is asynchronous
serial data standard, primarily used to allow a microprocessor to
communicate with other microprocessors or ICs such as memories, liquid crystal diodes (LCD), analog-to-digital converter
subsystems, etc. The SPI is a very simple synchronous serial
data, master/slave protocol based on four lines:
• SerialOutput(MOSI)
• SerialInput(MISO)
• SlaveSelect(SS)
1.1 SPI Protocol
Fig. 2:SPIwithSingleMasterandSingleSlave
1.1.1 SPI Signal Descriptions
Fig. 1: Block Diagram
Master In Slave Out (MISO): TheMISOlineisconfiguredas
MIT International Journal of Electronics and Communication Engineering, Vol. 4, No. 2, August 2014, pp. 65–69
ISSN 2230- 7672 © MIT Publications
an input in a master device and as an output in a slave device. It
is one of the two lines that transfer serial data in one direction,
alongwiththemostsignificantbitsentfirst.TheMISOlineof
a slave device is placed in the high-impedance state if the slave
is not selected.
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2. PGA DESIGN FLOW
2.1 Design Flow
TheISEdesignflowcomprisesthefollowingsteps:designentry,
design synthesis, design implementation, and Xilinx device programming.Designverification,whichincludesbothfunctional
Master Out Slave In (MOSI): TheMOSIlineisconfiguredas verificationand timingverification,takesplacesat different
output in a master device and as an input in a slave device. It points during the design flow.This section describes what to
is one of the two lines that transfer serial data in one direction, do during each step. For additional details on each design step,
withthemostsignificantbitsentfirst.
clickonalinkbelowthefollowingfigure.
Serial Clock (SCK): The serial clock is used to synchronize
datamovementbothinandoutofthedevicethroughitsMOSI
andMISOlines.TheMasterandSlavedevicesarecapableof
exchanging a byte of information during a sequence of eight
clock cycles. Since SCK is generated by the master device, this
line becomes an input on a slave device.
Slave Select (SS_bar): The slave select input line is used to
select a slave device. It has to be low prior to data transactions
and must stay low for the duration of the transaction.
SPI Data Transmission: The SPI has four modes of operation,
0 through 3. These modes essentially control the way data is
clocked in or out of an SPI device.
Fig. 4: FPGA Design Flow
Design Entry
Create an ISE project as follows:
1. Create a project.
2. Createfilesandaddthemtoyourproject,includingauser
constraints(UCF)file.
3. Addanyexistingfilestoyourproject.Assignconstraints
such as timing constraints, pin assignments, and area
constraints.
Fig. 3:SPIBusModes
3. DESIGN OF SPI
TheconfigurationisdonebytwobitsintheSPIcontrolregister 3.1 Master
(SPCR).TheclockpolarityisspecifiedbytheCPOLcontrolbit,
which selects an active high or active low clock. The clock phase
(CPHA) control bit selects one of the two fundamentally different transfer formats. To ensure a proper communication between
master and slave both devices have to run in the same mode. This
canrequireareconfigurationofthemastertomatchtherequirements of different peripheral slaves. SPI is a Synchronous data
transmission, clock plays important role in this Communication.
Fordescribingtheclockinformationwehavetwoflagscalled
CPOL and CPHA in SPI Control Register.The CPOL clock
polaritycontrolbitspecifiesanactivehighorlowclock.The
CPHA clock phase control bit selects one of two different transmission formats.
Fig. 5:SPIMaster
MIT International Journal of Electronics and Communication Engineering, Vol. 4, No. 2, August 2014, pp. 65–69
ISSN 2230- 7672 © MIT Publications
3.1.1 Features
3.2 Slave
• 3-to16-bitdatawidth
3.2.1 Features
• FourSPIoperatingmodes
• Bitrateupto9Mbps
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• 2to16-bitdatawidth
• 4SPImodes
• Dataratesto33Mb/s
3.1.2 General Description
3.2.2 General Description
TheSPIMaster component provides an industry-standard,
4-wire master SPI interface. It can also provide a 3-wire
(bidirectional) SPI interface. Both interfaces support all four
SPI operating modes, allowing communication with any SPI
slave device. In addition to the standard 8-bit word length, the
SPIMastersupportsaconfigurable3-to16-bitwordlengthfor
communicating with non standard SPI word lengths. SPI signals
includethestandardSerialClock(SCLK),MasterInSlaveOut
(MISO),MasterOutSlaveIn(MOSI),bidirectionalSerialData
(SDAT), and Slave Select (SS).
The SPI Slave provides an industry-standard 4-wire slave SPI
interface and 3-wire (or bidirectional) SPI mode. The interface
supports 4 SPI operating modes, allowing interface with any
SPI master device. In addition to the standard 8-bit interface,
theSPISlavesupportsaconfigurable2-to16-bitinterfacefor
interfacing to nonstandard SPI word lengths. SPI signals include
thestandardSCLK,MISO+MOSI(orSDAT)pinsandSlave
Select (SS) signal.
3.2.3 When to use the SPI Slave?
TheSPISlavecomponentshouldbeusedanytimethePSOC
deviceisrequiredtointerfacewithaSPIMasterdevice.Inad3.1.3 When to Use the SPI Master?
ditionto“SPIMaster”labeleddevicestheSPISlavecanbeused
SPIMasterComponentcanbeusedanytimethePSoCdevice with many devices implementing a shift register type interface.
must interface with one or more SPI slave devices. In addition TheSPIMastercomponentshouldbeusedininstancesrequiring
to“SPIslave”labeleddevices,theSPIMastercanbeusedwith thePSOCdevicetointerfacewithaSPISlavedevice.TheShift
many devices implementing a shift-register-type serial interface. Register component should be used in situations where its low
SPI Slave component can be used in instances in which the PSoC levelflexibilityprovideshardwarecapabilitiesnotavailablein
device must communicate with an SPI master device. The Shift the SPI Slave component.
Register component should be used in situations where its low3.2.4 Input/output Connections
levelflexibilityprovideshardwarecapabilitiesnotavailablein
This section describes the various input and output connections
theSPIMastercomponent.
fortheSPI.Anasterisk(*)inthelistofI/Oindicatesthatthe
I/Omaybehiddenonthesymbolundertheconditionslistedin
3.1.4 Input/Output Connections
thedescriptionofthatI/O.
This section describes the various input and output connections
fortheSPIcomponent.Anasterisk(*)inthelistofI/Osindicates 3.3 ON ChIP PERIPhERAL BUS
thattheI/Omaybehiddenonthesymbolundertheconditions
listedinthedescriptionofthatI/O.
Fig. 7:OnChipPeripheralBus
Fig. 6: Slave Block Diagram
OPBisdevelopedbyIBM.ItissomethinglikePCIonchip.
ItisanOn-Chipbusthatprovideslinkbetweentheprocessor
MIT International Journal of Electronics and Communication Engineering, Vol. 4, No. 2, August 2014, pp. 65–69
ISSN 2230- 7672 © MIT Publications
coreandotherperipherals.OPBisfullysynchronousandnon- 4.1 Slave:
multiplexed.Itsupports8-bit,16-bit,32-bit,64-bitslavesand
32-bit,64-bitmasters.
ThesinglecycletransferofdatatakesplacebetweenOPBbus
masterandOPBslaves.ThetransactioncarriedoutisPipelined
transaction. There are separate 32-bit read write buses and it
hasupto64bitaddressbus.ItisthemostusedPeripheralbus
for slower devices.
3.4 MASTER AND SLAvE COMMUNICATION
TheSPIprotocolbasicallydefinesabuswithfourwires(four
signals) and a common ground. There is one master device
controlling the activity on the bus, and one slave device. The
slave is active only when one of the signals, Slave Select (SS)
enables it. This signal is always provided by the master. There
can be more than one slave connected to the SPI bus, but each
slave requires its own Slave Select signal, see Fig. 1. The data
gets transferred serially bit by bit. There are basically two
signalstocarryinformation,onefrommastertoslave(MOSI,
MasterOutputSlaveInput,drivenbymaster),andoneforthe
oppositedirection(MISO,MasterInputSlaveOutput,drivenby
slave). The last signal SCLK (Serial CLocK) assures the time
synchronization between master and slave, and is always driven
by master. There are streamlined versions of the SPI bus using
only one signal to transfer data, but the direction of data must
be reversed on request; we will not use this kind of data transfer.
Fig. 9: RTL Schematic of Slave
Fig. 10:OutputofSlave
4.2 MASTER
Fig. 8:MastertoMultipleSlaveCommunication
4. SOFTWARE USED
For Synthesis and Implementation: Xilinx ISE (Integrated Software Environment) is a software tool produced by Xilinx for
synthesis and analysis of HDL designs, enabling the developer
to synthesize (“compile”) their designs, perform timing analysis,
examine RTL diagrams, simulate a design’s reaction to different
stimuli,andconfigurethetargetdevicewiththeprogrammer.
Starting the ISE Software
To start ISE, double-click the desktop icon, or start ISE from the
Start menu by selecting:
Fig. 11:RTLSchematicofMaster
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MIT International Journal of Electronics and Communication Engineering, Vol. 4, No. 2, August 2014, pp. 65–69
ISSN 2230- 7672 © MIT Publications
69
5. ADvANTAGES AND USES
Fast and easy. Fast for point-to-point connections. Easily allows
streaming/Constantdatainflow.Noaddressing/Simpletoimplement. Everyone supports it.
Itsupportsallfourmodes.TheMasterandSlaveareindependent of each other. It can be operated in Simplex, Duplex and
Full Duplex. It can be programmed at any frequency and at any
data width.
Uses: Some Serial Encoders/Decoders, Converters, Serial LCDs,
Sensors, etc. Pre-SPI serial devices PPC implements SPI well.
The bus of choice for communicating with small peripherals.
6. CONCLUSION
Fig. 12:OutputofMaster
The Design of Serial Peripheral Interface (SPI) with
Single Master and Single Slave configuratio nh asbeen
donesuccessfullyshowingthatitoperatesinSimplexMode.
This SPI master is a flexible programmable logic component
that accommodates communication with a variety of slaves via
a single parallel interface. It allows communication with a user
specifiednumberofslaves,whichmayrequireindependentSPI
modes, data widths, and serial clock speeds.
Thus, Designed SPI Protocol is used in Real Time application
of a SoC (System on chip) in order to communicate with the
PPC 440 Processor and other peripherals which is applicable for
present day Avionics Systems in Defense.
7. FUTURE SCOPE
Fig. 13:OutputofOPB
4.3 FINAL OUTPUT
ThecapabilitiesofanewflashmemoryinterfacefromSTMicroelectronics, which uses a Serial Peripheral Interface to access
serially,organizedflashnon-volatilememorydevicesoverwhat
it refers to as the SPI Flash Interface. SPI is now ubiquitous in
embedded designs, an integral element in microcontrollers and
FPGAs, and in applications in instrument panel clusters, digitally
controlled potentiometers, M2Mapplications, industrial controller area networks (CAN), temperature measurement and robotics.
REFERENCES
1. SPIBlockGuideV03.06, Free scale Semiconductor.
2. SPI Adapter with support of custom serial protocols, Byte Paradigm.
3. “ Tu l w a r t e c h n o l o g i e s o ff e r s F P G A d e s i g n s e r v i c e s ” .
Tulwartechnologies.com. 2013-01-21. Retrieved 2013-05-01.
4. McConnel, Toni,EETimes, “ESC - Xilinx All Programmable
System on a Chip combines best of serial and parallel processing.”
April 28, 2010. Retrieved February 14, 2011.
5. “Clock Generation”, Doulos, Retrieved 22 December 2012.
6. 1076-1987 – IEEE Standard VHDL Language Reference Manual.
1988.
Fig. 14:FinalOutput
doi:10.1109/IEEESTD.1988.122645. ISBN 0-7381-4324-3.