Semiconductor Manufacturing Technology: Semiconductor Manufacturing Processes Conrad T. Sorenson Praxair, Inc.

Semiconductor Manufacturing Technology:
Semiconductor Manufacturing Processes
Conrad T. Sorenson
Praxair, Inc.
 1999 Arizona Board of Regents for The University of Arizona
Sorenson
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
1
Semiconductor Manufacturing Processes
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Design
Wafer Preparation
Front-end Processes
Photolithography
Etch
Cleaning
Thin Films
Ion Implantation
Planarization
Test and Assembly
Wafer
Preparation
Design
Thin Films
Front-End
Processes
Photolithography
Ion
Implantation
Etch
Cleaning
Planarization
Test &
Assembly
Sorenson
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
2
Design
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Establish Design Rules
Circuit Element Design
Interconnect Routing
Device Simulation
Pattern Preparation
Wafer
Preparation
Design
Thin Films
Front-End
Processes
Photolithography
Ion
Implantation
Etch
Cleaning
Planarization
Test &
Assembly
Sorenson
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
3
Pattern Preparation
Reticle
Chrome Pattern
Pellicle
Quartz Substrate
Sorenson
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
4
Wafer Preparation
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Polysilicon Refining
Crystal Pulling
Wafer Slicing & Polishing
Epitaxial Silicon Deposition
Wafer
Preparation
Design
Thin Films
Front-End
Processes
Photolithography
Ion
Implantation
Etch
Cleaning
Planarization
Test &
Assembly
Sorenson
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
5
Polysilicon Refining
Chemical Reactions
Silicon Refining: SiO2 + 2 C  Si + 2 CO
Silicon Purification: Si + 3 HCl  HSiCl3 + H2
Silicon Deposition: HSiCl3 + H2  Si + 3 HCl
Reactants
H2
Silicon Intermediates
H2SiCl2
HSiCl3
Sorenson
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
6
Crystal Pulling
Quartz Tube
Rotating Chuck
Process Conditions
Flow Rate: 20 to 50 liters/min
Time: 18 to 24 hours
Temperature: >1,300 degrees C
Pressure: 20 Torr
Seed Crystal
Growing Crystal
(boule)
RF or Resistance
Heating Coils
Materials
Polysilicon Nodules *
Ar *
H2
Molten Silicon
(Melt)
Crucible
* High proportion of the total product use
Sorenson
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
7
Wafer Slicing & Polishing
silicon wafer
p+ silicon substrate
The silicon ingot is sliced into
individual wafers, polished, and
cleaned.
Sorenson
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
3/15/98
PRAX01C.PPT
Rev. 1.0
8
Epitaxial Silicon Deposition
silicon wafer
Susceptor
p- silicon epi layer
Gas
Input
p+ silicon substrate
Lamp
Module
Chemical Reactions
Silicon Deposition: HSiCl3 + H2  Si + 3 HCl
Process Conditions
Flow Rates: 5 to 50 liters/min
Temperature: 900 to 1,100 degrees C.
Pressure: 100 Torr to Atmospheric
Silicon Sources
SiH4
H2SiCl2
HSiCl3 *
SiCl4 *
Dopants
AsH3
B2H6
PH3
Etchant
HCl
Carriers
Ar
H2 *
N2
Quartz
Lamps
Wafers
Exhaust
* High proportion of the total product use
Sorenson
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
9
Front-End Processes
• Thermal Oxidation
• Silicon Nitride Deposition
- Low Pressure Chemical Vapor
Deposition (LPCVD)
• Polysilicon Deposition
- Low Pressure Chemical Vapor
Deposition (LPCVD)
• Annealing
Wafer
Preparation
Design
Thin Films
Front-End
Processes
Photolithography
Ion
Implantation
Etch
Cleaning
Planarization
Test &
Assembly
Sorenson
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
10
Front-End Processes
Vertical LPCVD Furnace
silicon dioxide (oxide)
Exhaust Via
Vacuum Pumps
and Scrubber
p- silicon epi layer
p+ silicon substrate
Chemical Reactions
Thermal Oxidation: Si + O2  SiO2
Nitride Deposition: 3 SiH4 + 4 NH3  Si3N4 + 12 H2
Polysilicon Deposition: SiH4  Si + 2 H2
Process Conditions (Silicon Nitride LPCVD)
Flow Rates: 10 - 300 sccm
Temperature: 600 degrees C.
Pressure: 100 mTorr
Oxidation Polysilicon Nitride
Annealing
Quartz Tube
3 Zone
Temperature
Control
Ar
H2
NH3 *
Ar
N2
N2
H2SiCl2 * He
H2O
SiH4 *
N2
H2
Gas Inlet
Cl2
AsH3
SiH4 *
N2
H2
B2H6
SiCl4
HCl *
PH3
* High proportion of the total product use
O2 *
Sorenson
Dichloroethene *
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
11
Photolithography
• Photoresist Coating Processes
• Exposure Processes
Wafer
Preparation
Design
Thin Films
Front-End
Processes
Photolithography
Ion
Implantation
Etch
Cleaning
Planarization
Test &
Assembly
Sorenson
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
12
Photoresist Coating Processes
photoresist
field oxide
p- epi
p+ substrate
Photoresists
Negative Photoresist *
Positive Photoresist *
Other Ancillary Materials (Liquids)
Edge Bead Removers *
Anti-Reflective Coatings *
Adhesion Promoters/Primers (HMDS) *
Rinsers/Thinners/Corrosion Inhibitors *
Contrast Enhancement Materials *
Developers
TMAH *
Specialty Developers *
Inert Gases
Ar
N2
Sorenson
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
13
Exposure Processes
photoresist
field oxide
p- epi
p+ substrate
Expose
Kr + F2 (gas) *
Inert Gases
N2
Sorenson
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
14
Ion Implantation
• Well Implants
• Channel Implants
• Source/Drain Implants
Wafer
Preparation
Design
Thin Films
Front-End
Processes
Photolithography
Ion
Implantation
Etch
Cleaning
Planarization
Test &
Assembly
Sorenson
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
15
Ion Implantation
phosphorus
(-) ions
junction
depth
Focus
Beam trap and
gate plate
Neutral beam and
beam path gated
photoresist mask
field oxide
n-w ell
p- epi
p-channel transistor
p+ substrate
Process Conditions
Flow Rate: 5 sccm
Pressure: 10-5 Torr
Accelerating Voltage: 5 to 200 keV
Gases
Ar
AsH3
B11F3 *
He
N2
PH3
SiH4
SiF4
GeH4
Neutral beam trap
and beam gate
Y - axis
scanner
X - axis
scanner
Wafer in wafer
process chamber
Equipment Ground
Resolving
Aperture
180 kV
Solids
Ga
In
Sb
Liquids
Al(CH3)3
Acceleration Tube
90° Analyzing Magnet
Terminal Ground
Ion Source
20 kV
* High proportion of the total product use
Sorenson
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
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Etch
• Conductor Etch
- Poly Etch and Silicon Trench
Etch
- Metal Etch
• Dielectric Etch
Wafer
Preparation
Design
Thin Films
Front-End
Processes
Photolithography
Ion
Implantation
Etch
Cleaning
Planarization
Test &
Assembly
Sorenson
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
17
Conductor Etch
source-drain areas
gate linew idth
gate oxide
p-w ell
n-w ell
p-channel transistor n-channel transistor
p+ substrate
Chemical Reactions
Silicon Etch: Si + 4 HBr  SiBr4 + 2 H2
Aluminum Etch: Al + 2 Cl2  AlCl4
Process Conditions
Flow Rates: 100 to 300 sccm
Pressure: 10 to 500 mTorr
RF Power: 50 to 100 Watts
Polysilicon Etches
HBr *
C2F6
SF6 *
NF3 *
O2
Aluminum Etches
Cluster Tool
Configuration
Wafers
Etch
Chambers
Transfer
Chamber
Loadlock
RIE Chamber
Transfer
Chamber
Gas Inlet
Wafer
RF Power
BCl3 *
Cl2
Diluents
Ar
He
N2
Exhaust
* High proportion of the total product use
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Sorenson
18
Dielectric Etch
Contact locations
Cluster Tool
Configuration
p-w ell
n-w ell
p-channel transistor n-channel transistor
p+ substrate
Wafers
Chemical Reactions
Oxide Etch: SiO2 + C2F6  SiF4 + CO2 + CF4 + 2 CO
Process Conditions
Flow Rates: 10 to 300 sccm
Pressure: 5 to 10 mTorr
RF Power: 100 to 200 Watts
Plasma Dielectric Etches
CHF3 *
CF4
C2F6
C3F8
CO *
CO2
O2
SF6
SiF4
Diluents
Etch
Chambers
Transfer
Chamber
Loadlock
RIE Chamber
Transfer
Chamber
Ar
He
N2
Gas Inlet
Wafer
RF Power
Exhaust
* High proportion of the total product use
Sorenson
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
19
Cleaning
• Critical Cleaning
• Photoresist Strips
• Pre-Deposition Cleans
Wafer
Preparation
Design
Thin Films
Front-End
Processes
Photolithography
Ion
Implantation
Etch
Cleaning
Planarization
Test &
Assembly
Sorenson
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
20
Critical Cleaning
Contact locations
p-w ell
n-w ell
p-channel transistor n-channel transistor
p+ substrate
1
Process Conditions
Temperature: Piranha Strip is 180 degrees C.
1 Organics
H2SO4 +
H2O2
H2O Rinse
RCA Clean
SC1 Clean (H2O + NH4OH + H2O2) *
* SC2 Clean (H2O + HCl + H2O2) *
Piranha Strip
* H2SO4 + H2O2 *
Nitride Strip
H3PO4 *
Oxide Strip
HF + H2O *
2
2 Oxides
HF +
H2O
H2O Rinse
Dry Strip
N2O
O2
CF4 + O2
O3
3
4
3 Particles
4 Metals
NH4OH +
HCl +
H2O2 + H2O
H2O2 + H2O
H2O Rinse
H2O Rinse
5
5 Dry
H2O or IPA +
N2
Solvent Cleans
NMP
Proprietary Amines (liquid)
Dry Cleans
HF
O2 Plasma
Alcohol + O3
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Sorenson
21
Thin Films
• Chemical Vapor Deposition
(CVD) Dielectric
• CVD Tungsten
• Physical Vapor Deposition
(PVD)
• Chamber Cleaning
Wafer
Preparation
Design
Thin Films
Front-End
Processes
Photolithography
Ion
Implantation
Etch
Cleaning
Planarization
Test &
Assembly
Sorenson
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
22
Chemical Vapor Deposition (CVD) Dielectric
Metal 1
insulator layer 2
p-w ell
n-w ell
p-channel transistor n-channel transistor
p+ substrate
Metering
Pump
Inert Mixing
Gas
TEOS
Source
Chemical Reactions
Si(OC2H5)4 + 9 O3  SiO2 + 5 CO + 3 CO2 + 10 H2O
Process Conditions (ILD)
Flow Rate: 100 to 300 sccm
Pressure: 50 Torr to Atmospheric
Vaporizer
Direct
Liquid
Injection
LPCVD
Chamber
CVD Dielectric
O2
O3
TEOS *
TMP *
Transfer
Chamber
Process Gas
Gas Inlet
Wafer
RF Power
Exhaust
* High proportion of the total product use
Sorenson
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
23
Chemical Vapor Deposition (CVD) Tungsten
titanium
tungsten
Input
Cassette
p-w ell
n-w ell
p-channel transistor n-channel transistor
p+ substrate
Chemical Reactions
WF6 + 3 H2  W + 6 HF
Process Conditions
Flow Rate: 100 to 300 sccm
Pressure: 100 mTorr
Temperature: 400 degrees C.
CVD Dielectric
WF6 *
Ar
H2
N2
Output
Cassette
Wafer
Hander
Wafers
Multistation Sequential
Deposition Chamber
Water-cooled
Showerheads
Resistively
Heated Pedestal
* High proportion of the total product use
Sorenson
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
24
Physical Vapor Deposition (PVD)
Physical
Vapor
Deposition
Chambers
Cluster Tool
Configuration
p-w ell
n-w ell
p-channel transistor n-channel transistor
p+ substrate
Process Conditions
Pressure: < 5 mTorr
Temperature: 200 degrees C.
RF Power:
Wafers
Transfer
Chamber
Loadlock
Reactive
Gases
PVD Chamber
N
Barrier Metals
SiH4
Ar
N2
N2
Ti PVD Targets *
Transfer
Chamber
Argon &
Nitrogen
S
N
Cryo Pump
e+
Wafer
Backside DC Power
He Cooling Supply (+)
* High proportion of the total product use
Sorenson
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
25
Chamber Cleaning
Multistation Sequential
Deposition Chamber
Water-cooled
Showerheads
Resistively
Heated Pedestal
Chemical Reactions
Oxide Etch: SiO2 + C2F6  SiF4 + CO2 + CF4 + 2 CO
Process Conditions
Flow Rates: 10 to 300 sccm
Pressure: 10 to 100 mTorr
RF Power: 100 to 200 Watts
Aluminum
Surface Coating
Chamber Cleaning
C2F6 *
NF3
ClF3
Process Material Residue
Chamber Wall Cross-Section
* High proportion of the total product use
Sorenson
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
26
Planarization
• Oxide Planarization
• Metal Planarization
Wafer
Preparation
Design
Thin Films
Front-End
Processes
Photolithography
Ion
Implantation
Etch
Cleaning
Planarization
Test &
Assembly
Sorenson
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
27
Chemical Mechanical Planarization (CMP)
Platen
Head
Sweep Slide
p-w ell
n-w ell
p-channel transistor n-channel transistor
p+ substrate
Load/Unload
Station
Process Conditions (Oxide)
Flow: 250 to 1000 ml/min
Wafer Handling
Robot & I/O
Particle Size: 100 to 250 nm
Concentration: 10 to 15%, 10.5 to 11.3 pH
Process Conditions (Metal)
Flow: 50 to 100 ml/min
Wafer
Particle Size: 180 to 280 nm
Carrier
Concentration: 3 to 7%, 4.1 - 4.4 pH
Backing (Carrier) Film CMP (Oxide)
Polyurethane
Pad
Polyurethane
Pad Conditioner
Abrasive
Silica Slurry *
KOH *
NH4OH
H2O
CMP (Metal)
Polishing
Head
Pad
Conditioner
Carousel
Polishing Pad
Slurry
Delivery
Wafer
Platen
Alumina *
* High proportion of the total product use.
Sorenson
FeNO3
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
28
Test and Assembly
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•
•
•
Electrical Test Probe
Die Cut and Assembly
Die Attach and Wire Bonding
Final Test
Wafer
Preparation
Design
Thin Films
Front-End
Processes
Photolithography
Ion
Implantation
Etch
Cleaning
Planarization
Test &
Assembly
Sorenson
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
29
Electrical Test Probe
bonding pad
nitride
Metal 2
p-well
n-well
n-channel
transistor
p-channel transistor
p+ substrate
Defective IC
Individual integrated circuits
are tested to distinguish good
die from bad ones.
Sorenson
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
30
Die Cut and Assembly
Good chips are attached
to a lead frame package.
Sorenson
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
31
Die Attach and Wire Bonding
lead frame
gold wire
bonding pad
connecting pin
Sorenson
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
32
Final Test
Chips are electrically
tested under varying
environmental conditions.
Sorenson
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
33
References
1.
2.
3.
4.
5.
6.
7.
8.
CMOS Process Flow in Wafer Fab, Semiconductor Manufacturing Technology, DRAFT,
Austin Community College, January 2, 1997.
Semiconductor Processing with MKS Instruments, Inc.
Worthington, Eric. “New CMP architecture addresses key process issues,” Solid State
Technology, January 1996.
Leskonic, Sharon. “Overview of CMP Processing,” SEMATECH Presentation, 1996.
Gwozdz, Peter. “Semiconductor Processing Technology” SEMI, 1997.
CVD Tungsten, Novellus Sales Brochure, 7/96.
Fullman Company website. “Fullman Company - The Semiconductor Manufacturing
Process,” http://www.fullman.com/semiconductors/index.html, 1997.
Barrett, Craig R. “From Sand to Silicon: Manufacturing an Integrated Circuit,” Scientific
American Special Issue: The Solid State Century, January 22, 1998.
Sorenson
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
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