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Busser
Dette kompendium er et forsøg på at beskrive nogle af de forskellige busser, der anvendes inden for
elektronikken til kommunikation imellem uC’er, ICér og PC-er.
Kompendiet er ikke færdigt, - men bearbejdes løbende:
De busser, der i dette materiale hovedsagelig er tale om er:
RS232, RS485, 1-Wire, I2C, 3-wire, SPI, MicroWire
Se evt:
Youtube: https://www.youtube.com/watch?v=7KoyvfTYpno
/: Valle Thorø
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Ældre Bussystemer: Centronic og RS232
Mellem gamle PC-er og fx en printer foregik
kommunikationen enten parallelt eller serielt. Parallelprotokollen hedder Centronic, og er en 8 bit parallel
overførsel, plus forskellige kontrol-signaler, såkaldte
handshake-signaler. Der blev brugt et 25 pin canon-stik. ??
( 8 bit parallel-port )
En anden måde at sende signaler til en printer var via en seriel
forbindelse, kaldet RS232.
Nu til dags findes disse stik ikke på vore PC-er. Der bruges i stedet fx USB-stik.
Mange fysikapparater har hidtil været koblet til PC-ere via RS232-stik. Så her er man nødt til at
lave noget konvertering fra RS232 til USB.
Der kan købes konvertere, der omdanner USB- til RS232. Der
findes også USB til andre serielle protokoller, endog
konvertere til parallel Centronic protokol findes! Dvs. ældre
udstyr godt kan kobles på en USB-port.
For at få konverteren til at virke, skal der installeres nogle
drivere, og de får PC-en til at ”tro”, at den har en ny
hardware-port installeret.
Se evt. et specielt kompendium herom!!
Nyere bussystemer:
De bussystemer, der er forsøgt beskrevet her, er serielle systemer, der kan bruges direkte mellem
microcontrollere.
/: Valle Thorø
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På flg. links findes en fin sammenligning af forskellige bussystemer.
http://www.embedded.com/design/connectivity/4023975/Serial-Protocols-Compared
http://www.maximintegrated.com/app-notes/index.mvp/id/3967
Fra Microcontroller til microcontroller. TxD RxD
I “vores” microcontroller, 8051 eller ATMEGA328, som bruges i Arduino Uno, er der indbygget en
UART, der står for Universal Asynkron Receiver Transmitter. Denne kan både sende og modtage
serielle signaler. Dette betyder, at 2 uC’er kan kobles sammen.
Data kan sendes både:
Synkron
Der sendes både et signal plus et clock-signal, så modtageren ved, når der
skal klockes ind i et skifteregister. Der skal bruges 2 signal-ledninger, - og
fælles stel, Gnd, dvs. i alt 3 ledninger.
Asyncron
Data afsendes og kommer til modtageren på et tilfældigt tidspunkt. Derfor
skal der være ”aftalt” en protokol, dvs. at startbit, stopbit, baudrate osv. skal
være kendt.
Det er nok med 1 signalledning, plus nul.
I vores 8-bit uC sendes ”pakker” eller bytes asynkront. Der sendes 1 Startbit, 8 databit, og 1 stopbit.
Signaler kan sendes direkte fra uC til uC, dvs.
med signalniveauer på 0 og 5 Volt. Tx fra den
ene uC skal forbindes til Rx på den anden uC.
Dette medfører dog ret begrænset rækkevidde
pga. evt. støjpåvirkning, der kan medføre at
signalet forvanskes så modtageren læser forkert.
Men det kan sagtens bruges til at koble to uC
sammen på samme print og over kortere
afstande. Fx kan man lade én uC kontrollere et
tastatur, og sende de indtastede data til en anden
uC via UART´en.
/: Valle Thorø
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Til højre ses et eksempel på et scoop-billede af
tre byte, sendt direkte fra en uC.
RS232
Ønskes større rækkevidde, kan man bruge
”protokollen” der kaldes RS232. Her bruges
lidt højere spændinger i signalet end de 5
Volt direkte fra uC’en, og ”omvendt
polaritet”.
Der findes kredse, der selv via
ladningspumpe-princippet genererer
plus/minus 12 Volt. Fx Max232 fra Maxim.
Et ”1”-tal sendes som minus 12 volt, og et ”0” som plus 12 volt.
( Valide spændinger er dog mellem ± 3 og 12 Volt. )
Her ses en graf over
signalerne i en
transmission af en
pakke på 8 databit efter
RS232-standarden.
Evt. kan sendes en 9.
bit, en Paritetsbit.
Transmissionsafstanden
er dog ikke garanteret
over ca. 10 meter!
Grafen er fra: http://en.wikipedia.org/wiki/RS-232
/: Valle Thorø
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De data, dvs. de 8 bit-pakker, der blev brugt til at sende data til printere efter RS232 - standarden i
”gamle dage” var ordnet efter ASCII-tabellen.
Opgave:
Tjek kredsen MAX232, der kan bruges til at omforme fra 5 Volt signaler til +/- 12 Volt.
I RS232 protokollen sendes signalet på 1 ledning, men en nul-ledning skal også forbindes. Tillige
bruges evt. et antal handshake-signaler, til fx at fortælle afsenderen, at modtageren er optaget, dvs.
Busy, – eller at den ikke er færdig med at behandle de forrige data !!.
RS485
Ønskes en meget stabil og meget langtrækkende signaloverførsel, kan man med fordel vælge at
bruge standarden kaldet RS485.
Igen bruges eksterne IC-er til at
omforme et serielt signal, der
skal sendes mellem to uC-er.
Her ses et eksempel på hvordan flere
sendere / modtagere kan kobles sammen
på et RS485-netværk.
Hver RS485 kreds er forbundet til en
uC.
I eksemplet her er vist, at der kan kobles
flere uC-er sammen på samme bus.
/: Valle Thorø
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Standarden RS485 benytter et balanceret signal, på kun 2-ledere. Stel
skal ikke med.
Rækkevidden er ca. op til 1 km. med en spænding på blot 5 Volt. Det
er dog en betingelse, at lederne er snoede, for at modvirke indstrålet
elektrisk støj.
Til at kode og til at afkode signalet bruges en lille IC. De to ledninger i
bussen kaldes for A og B. De forbindes til kredsens A og B-terminaler.
Kredsen LTC485
Eller DS75176
Eller ADM485
Kredsen kan kobles som enten sender eller modtager.
Parsnoning modvirker støj:
De blå pile på tegningen repræsenterer indstrålet
magnetfelt, og de sorte den inducererede strøm.
På nederste billede ses, at hvis ledningerne er
snoet kabel ophæves støj-påvirkningen.
Billede fra : http://www.lammertbies.nl/comm/info/RS-485.html
In the picture above, noise is generated by magnetic fields from the environment. The picture
shows the magnetic field lines and the noise current in the RS485 data lines that is the result
of that magnetic field. In the straight cable, all noise current is flowing in the same direction,
practically generating a looping current just like in an ordinary transformer. When the cable is
twisted, we see that in some parts of the signal lines the direction of the noise current is the
oposite from the current in other parts of the cable. Because of this, the resulting noise
current is many factors lower than with an ordinary straight cable.
http://www.lammertbies.nl/comm/info/RS-485.html
Each of the four pairs in a Cat 5 cable has differing precise number of twists per meter to
minimize crosstalk between the pairs
Individual twist lengths
By altering the length of each twist, crosstalk is reduced, without affecting the characteristic
impedance. The distance per twist is commonly referred to as pitch, twist rate or twist
periodicity.
http://en.wikipedia.org/wiki/Category_5_cable
Twist længder er fx. 1,53 til 1,94 cm pr twist.
/: Valle Thorø
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http://www.windmill.co.uk/rs485.html
Normalt er et RS-485 modtagers output "1" hvis
spændingen på A er mere end 200mV højere end
på B, og "0" hvis B > A med 200mV eller mere.
RS485-bussen sender data differential over et
twisted pair kabel. Dvs. at når den ene ledning
bliver positiv, bliver den anden nul, og modsat.
Kablet skal termineres med 120 Ohm i hver
ende.
Kilde:
http://www.maxim-ic.com/appnotes.cfm/an_pk/723/
Her ses en anden graf over signalerne:
Transmitterens spænding er ”høj” i forhold til
den nødvendige spænding for modtageren.
Herved opnås også støjimmunitet.
Det højre billede viser signalets
spændingsniveauer på sendersiden
sammenlignet med den større tolerance på
modtagersiden.
/: Valle Thorø
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IC-Kredsen til RS485-kommunikation har en enable til at
koble output-trinnet og TxD ind. Er kredsen ikke enablet,
er output-trinnet højimpedant.
Et digitalt signal på input konverteres til et differential
signal på bussen. Et højt ( logisk 1 ) svarer til at de to
output-ledninger har UA større end UB. Et logisk 0 er
modsat. UB > UA.
I RS485 kan bruges bus-frekvenser op til 12 Mbits/s.
Max buslængde afhænger af overførselshastigheden. Den absolut største længde er 1200 meter ved
en datarate på 93,7 Kbit/s med max 32 enheder på bussen. Ved hjælp af repeatere, dvs.
signalforstærkere, kan der kobles 4 grupper a’ 32 devices sammen. Eksempler på RS485-interfacekredse er SN75176 fra Texas og MAX485 fra Maxim.
En regel for standard kabler lyder, at Baudraten ganget med kabel-længden i meter skal være mindre
end 10^8. Så fx, hvis et kabel er 100 meter lang, fås en max baudrate på 1Mbit/s.
Man behøver ikke altid at bruge TP-kabler. Ved små afstande er alm. telefonkabler gode nok.
Terminering på 120 ohm i begge ender behøves ikke altid ved små længder kabel.
Simplex
Ved simplex sendes kun i den
ene retning ad gangen.
/: Valle Thorø
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Duplex
Skal der sendes i begge retninger
samtidigt, må man bruge IC’er, der
kan håndtere det, - eller evt. 4 alm.
8-pins LTC485.
Figuren viser et
twisted par med
terminering.
http://www.maxim-ic.com/app-notes/index.mvp/id/763
Der bruges normalt
termineringsmodstande på 120
Ohm. Svarende til kablets
impedans.
Pins skal forbindes som flg.:
LTC485, DS75176,
Koblet som:
Pin
Pin
Sender Modtager
Reciever Out
1
NC
Rx
Reciever
Out
enable
2
5V
0
3 Driver output enable
5V
0
4
Driver input
Tx
0
5
GND
0
0
6
Signal
A
A
7
Signal
B
B
8
Vcc
5V
5V
http://pdf1.alldatasheet.net/datasheet-pdf/view/8465/NSC/DS75176.html
/: Valle Thorø
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Her et billede fra et Scoop-billede af de to
signaler:
http://www.maxim-ic.com/app-notes/index.mvp/id/723
Læs evt. mere: http://www.emcu.it/MCUandPeriph/RS485/RS485uk.html
RS 485 exists in two versions: 1 TwistedPair or 2 TwistedPairs.

Single TwistedPair RS 485
In this version, all devices are connected to a single TwistedPair. Thus, all of them must
have drivers with tri-state outputs (including the Master). Communication goes over the
single line in both directions. It is important to prevent more devices from transmitting at
same time (software problem).

Double TwistedPair RS 485
Here, Master does not have to have tri-state output, since Slave devices transmit over the
second twistedpair, which is intended for sending data from Slave to Master.
Sometimes you can see a RS 485 system in a point-to-point system. It is virtually identical
to RS 422; the high impedance state of the RS 485 output driver is not used. The only
difference in hardware of the RS 485 and RS 422 circuits is the ability to set the output to
high impedance state.
http://www.pccompci.com/The_RS-_485_Serial_Port.html
I2C, I2C, IIC, eller 2-wire-bus.
Bussen I2C har flere navne. IIC står for “Inter IC Communications” eller Inter Integrated
Controller. Den kaldes også nogle steder for 2-wire bus.
/: Valle Thorø
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Se video på dette link: http://tronixstuff.com/2010/10/20/tutorial-arduino-and-the-i2c-bus/
I2C bussen er skabt af Philips I 80érne. Dengang var standarden en max clockfrekvens på 100 KHz,
men nu findes en hurtigere standard på 400 KHz.
I2C-bussen er en bus, hvor to
signal-ledninger bruges til at
sende signaler til et antal
tilkoblede IC-er.
Der skal bruges 2 signalledere
og en nul-leder.
Denne skitse illustrerer hvordan IC-erne
koblet på bussen kan trække signalet lavt med
en Open Collector eller Open Drain.
http://www.scribd.com/doc/77997878/Final-Project
/: Valle Thorø
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I2C er en standard bidirektionel 2 wire-bus, der bruges til kommunikation mellem chips i moderne
elektronisk udstyr, fx i et TV gemmes opsætninger af kanaler osv. i EEPROM’s via IIC-bussen.
Vha. bussen kan man forbinde en uC til fx en seriel EEPROM, Temperatur IC, port-kredse osv.
Alle de tilkoblede kredse kaldes slaver.
Al kommunikation sker med et clock-signal og et data-signal. Plus selvfølgelig stel.
Bussen bruges kun til at koble et antal kredse til en kontroller internt på et printkort. Ikke til
kommunikation ”længere væk”.
Det ses, at der kun anvendes 2 wires, der
forbindes til alle enhederne i systemet. Plus
selvfølgelig nul. Dette er ret smart, idet der så
ikke optages et antal pins i controlleren for hver
tilkoblet kreds.
I andre bussystemer angiver processoren med en
separat ledning til hver tilsluttet kreds, - en Chip
Select, - at den er interesseret i at kommunikere
med netop denne kreds.
Men i I2C-systemet sker dette valg af tilsluttede kredse også på de to signalledninger.
Kredsene er født med en ”unik” ID-kode, også kaldet slaveadresse. Den består af en bit kode som
masteren sender ud på bussen. Koden kan være mellem 4 til 7 bit.
De tilsluttede kredse vil derfor kun reagere, når processoren ”kalder dem op” ved at sende deres IDkode.
I I2C-bussen findes der
ingen chipselect. De
enkelte chips på bussen
kaldes op ved deres
adresse eller ID.
Adressen er ( normalt ) 7
bit – og det 8. bit
bestemmer, om man
kalder chippen op for
skrive eller læseadgang.
Eksempel med EEPROM
/: Valle Thorø
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Control Byte Allocation { 24LC256 EEPROM }
1
0
1
0
A2
A1
A0
R/W
Den her viste en IC, en EEPROM, har kun en 4-bit ID. De 4 mest betydende bit i Slaveadressen er
bestemt af fabrikanten, og de næste 3 bit er ført ud til pins, hvilket bevirker, at man fx med
dipswitche kan bestemme 3 af IC-ens adressebit. Herved kan man sætte hele 8 af samme IC på
bussen.
Pin’ene kaldes A2, A1 & A0.
Forbindelserne ser fx således ud!!
IC-ens ID, kan aflæses i dens
datablad.
Den samlede ID bliver altså
???? 000 r/w,
The pull-up resistors are required
and can vary from 4.7k to 10k.
Følgende skema angiver forskellige kredstyper og deres ID-kode. ( Eller adresser )
Nogle af kredsene flere end 4 bit ID.
/: Valle Thorø
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Nogle kredse er i dag så store, fx EEPROM’s, at der i kredsen er større memory, end der kan vælges
eller adresseres med 8 bit. For disse kredse er memory’en opdelt i BANKS, eller afdelinger. Her kan
A2, A1 og A0 opfattes som Bank-valg, i stedet for IC-valg. Afhængig af størrelse kan der så kobles
et færre antal kredse på bussen.
En kreds adresseres så med en byte bestående af 4 bit ID, og 3 bit device, (eller Bank).
Det kunne se sådan ud!
IC type ID
1
0
0
/: Valle Thorø
1
A2
Kreds / Bank
A1
A0
R/W
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En kommunikation fra en controller foregår på den måde, at controlleren først udsender en “start”.
Herefter udsendes en ID-byte, der får den rette IC-enhed til at reagere. I byten er med bit 0 angivet,
om der ønskes læse eller skriveadgang. ( R / W )
Den kreds, der adresseres, svarer efterfølgende ved at sende et ACKnoledge signal.
Ønskes fx at gemme noget i en EEPROM, sendes der fra controlleren efterfølgende fx den adresse i
EEPROM’en, hvor der skal gemmes. Igen kvitterer kredsen, der også kaldes ”slaven” med en ACK.
Næste byte, controlleren sender gemmes så på korrekte plads.
Når controlleren er færdig, sendes en STOP ordre.
Dette er illustreret i følgende skitse.
Det er også mulig at sende flere på
hinanden følgende databyte.
Først når der sendes en Stop-kommando fra
controlleren, er transmissionen færdig.
Her følger flere timing-diagrammer:
http://pdf1.alldatasheet.com/datasheet-pdf/view/106552/ISSI/IS24C16.html
/: Valle Thorø
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http://pdf1.alldatasheet.com/datasheet-pdf/view/106552/ISSI/IS24C16.html
http://www.ti.com/lit/ml/slap117/slap117.pdf
På internettet kan findes nogle ( få ) I2C-primitives, der skal opfattes som små programstumper,
eller subrutiner. Disse kan kopieres og anvendes i en kilde-tekst. Det er fx Start, Stop, Sendbyte,
Modtagbyte osv. Se mere senere!!
Hovedprogrammets opgave er så at flytte data i rigtige RAM-registre i controlleren før der sker et
kald til I2C-programstumperne. ( for 8051 og Assembler-programmering )
I Arduinoverdenen findes biblioteksprogrammer til kommunikationen.
Acknoledge kan opfattes som det 9. bit, hvor slaven trækker dataledningen lav.
Der findes større kredse, hvor det er nødvendigt at sende 2 adressebytes.
Det er ikke nødvendigt, at opretholde en konstant klockfrekvens. Derfor kan processoren godt
servicere interruptrutiner undervejs.
Se evt. tysk kodegenerator.
/: Valle Thorø
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Der findes ny protokol med 10 bit adressing og op til 400 Kbit / sek.
Diverse I2C-Kredse:
Følgende en oversigt over nogle forskellige relevante I2C-kredse.
Type
PCF8574
PCF8574A
DS 1624
Forklaring
8 bit Port expander Read / Write ( Read, = læs port til uC )
Port expander Read / Write ( Read, = læs port til uC ), Anden ID-kode !!
Temperaturcensoren fra Dallas kan indstilles til forskellige temperaturmodes, enten
kontinuerlig, eller sleepmode, med startsignal hver gang der ønskes en konvertering.
PCF8591
DS1307
100 KHz 4 kanal 8 bit ADC
Real time clock
Her et par gaflede tekster, der på fin vis forklarer baggrunden for IIC-protokollen:
I2C Baggrund
I2C, or 2-wire
communication, is a form of
synchronous serial
communication that was
developed by Phillips
Semiconductor. Two wires,
serial data (SDA) and serial
clock (SCL), carry information
between the devices
connected to the bus. Each
byte put on the SDA line
must be 8-bits long, but the
number of bytes transmitter
per transfer is unrestricted.
Term
Definition
Transmitter
The device which is currently sending data
to the buss.
Receiver
The device which is currently receiving
data from the buss.
Master
The device which initiates a transfer,
generates clock signals and terminates a
transfer. In our case, this is always the
BS2.
Slave
The device addressed by the MASTER.
Both SDA and SCL are bi-directional lines, connected to a positive supply voltage via a pull-up
resistor (usually between 4.7k and 10k). When the bus is free, both lines are high. Each device
is recognized by a unique address (whether it's an EEPROM, RTC or I/O expander) and can
operate as either a transmitter or receiver. In addition to transmitters and receivers, devices
can also be considered as masters or slaves when performing data transfers. The BASIC Stamp
cannot operate as an I2C slave device, however. The table below defines I2C terminology:
All I2C communication must begin with a START condition and terminate with a STOP
condition. START and STOP conditions are generated by the master and are defined as:
/: Valle Thorø
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START
STOP
A HIGH to LOW transition of
the SDA line while SCL is
HIGH indicates a START
condition.
A LOW to HIGH transition of
the SDA line while SCL is
HIGH defines a STOP
condition.
After a START condition, a control byte is sent. The control byte consists of a unique 7-bit
device address and a R/W (read/write) bit. If R/W is a logic 1, a READ command is sent and if
R/W is a logic 0, a WRITE command is sent. Some devices, such as serial EEPROM, have "A"
address pins which allow you to change the address of a device. For example, an EEPROM with
A2, A1, A0 connected to ground would have a address of 1010000 while an EEPROM with A2,
A1, A0 connected to +5v would have an address of 1010111. Using these address pins, up to 8
identical devices can be configured to share the same I2C bus.
Control Byte Allocation { 24LC256 EEPROM }
1
0
1
0
A2
A1
A0
R/W
Some devices, such as the 24LC16B, are not internally connected to these address pins.
Instead, these bits in the control byte function as "page selection blocks," usually denoted as
b2, b1, b0. The 24LC16B is configured as a 8x256 device with 8 blocks, or pages, of memory.
B2, B1, B0 is used to select a page ranging from 0 - 7.
Control Byte Allocation for devices which use block
selection { 24LC16B EEPROM }
1
0
1
0
B2
B1
B0
R/W
After the control byte is sent, the receiver sends an acknowledgement ("ACK") to the
transmitter. During the 9th clock pulse on SCL (generated by the MASTER), the transmitter
must release the SDA line which the receiver then must pull down (LOW). This LOW on SDA
(generated by the SLAVE) is an ACK. After the transmitter receives the ACK, data can be sent.
An ACK is usually sent after each byte of data.
EEPROM can be read from or written to in a number of ways (byte write, page write, current
read, random read, sequential read) depending on the particular device. For the purposes of
this tutorial, we are going to focus on byte write and random read. The sample software below
contains examples for all five methods of reading and writing.
Byte Write
Byte write is used to put data into a specific memory location. Following the START condition
from the master, a control byte with R/W set to logic 0 (WRITE) is clocked onto the bus by the
master transmitter. This indicates to the slave that the address high byte will follow after it has
generated an ACK. After the ACK is received, the high byte of the address is sent, and ACK is
received, the low byte of the address is sent, an ACK is received, the data is sent, an ACK is
received and finally a STOP condition from the master terminated communication. (Do you see
a pattern with ACK?)
/: Valle Thorø
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Current Address Read
Current address read will read the data at the current address of the EEPROM's internal
address pointer. If the previous read was at location "n", the next current address read would
access data from address "n+1". A control byte with R/W set to logic 1 (READ) is sent by the
Master, the Master receives the slave's ACK, the Master gets the DATA and issues a STOP
condition without generating an ACK. This is called a "NACK".
Random Read
Random read will access data from a specified EEPROM address. Random read is very similar
to byte write with one exception: where the data is sent in Byte Write, Random Read sends a
START condition with R/W set to logic 1 (READ), receives the ACK and the data, then issues a
NACK (a STOP condition without sending an ACK).
Følgende er fra http://www.robot-electronics.co.uk/acatalog/I2C_Tutorial.html er gaflet:
The I2C Physical Protocol
When the master (your controller) wishes to talk to a slave (our CMPS03 for example) it begins by issuing a start sequence on
the I2C bus. A start sequence is one of two special sequences defined for the I2C bus, the other being the stop sequence. The
start sequence and stop sequence are special in that these are the only places where the SDA (data line) is allowed to change
while the SCL (clock line) is high. When data is being transferred, SDA must remain stable and not change whilst SCL is high.
The start and stop sequences mark the beginning and end of a transaction with the slave device.
Data is transferred in sequences of 8 bits. The bits are placed on the SDA line starting with the MSB (Most Significant Bit). The
SCL line is then pulsed high, then low. Remember that the chip cannot really drive the line high, it simply "lets go" of it and the
resistor actually pulls it high. For every 8 bits transferred, the device receiving the data sends back an acknowledge bit, so there
are actually 9 SCL clock pulses to transfer each 8 bit byte of data. If the receiving device sends back a low ACK bit, then it has
received the data and is ready to accept another byte. If it sends back a high then it is indicating it cannot accept any further
data and the master should terminate the transfer by sending a stop sequence.
How fast?
The standard clock (SCL) speed for I2C up to 100KHz. Philips do define faster speeds: Fast mode, which is up to 400KHz and
High Speed mode which is up to 3.4MHz. All of our modules are designed to work at up to 100KHz. We have tested our
modules up to 1MHz but this needs a small delay of a few uS between each byte transferred. In practical robots, we have never
had any need to use high SCL speeds. Keep SCL at or below 100KHz and then forget about it.
I2C Device Addressing
All I2C addresses are either 7 bits or 10 bits. The use of 10 bit addresses is rare and is not covered here. All of our modules and
the common chips you will use will have 7 bit addresses. This means that you can have up to 128 devices on the I2C bus, since
a 7bit number can be from 0 to 127. When sending out the 7 bit address, we still always send 8 bits. The extra bit is used to
inform the slave if the master is writing to it or reading from it. If the bit is zero the master is writing to the slave. If the bit is 1 the
master is reading from the slave. The 7 bit address is placed in the upper 7 bits of the byte and the Read/Write (R/W) bit is in
the LSB (Least Significant Bit).
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The I2C Software Protocol
The first thing that will happen is that the master will send out a start sequence. This will alert all the slave devices on the bus
that a transaction is starting and they should listen in incase it is for them. Next the master will send out the device address. The
slave that matches this address will continue with the transaction, any others will ignore the rest of this transaction and wait for
the next. Having addressed the slave device the master must now send out the internal location or register number inside the
slave that it wishes to write to or read from. This number is obviously dependent on what the slave actually is and how many
internal registers it has. Some very simple devices do not have any, but most do.
Having sent the I2C address and the internal register address the master now can send the data byte (or bytes, it doesn't have
to be just one). The master can continue to send data bytes to the slave and these will normally be placed in the following
registers because the slave will automatically increment the internal register address after each byte. When the master has
finished writing all data to the slave, it sends a stop sequence which completes the transaction.
So to write to a slave device:
1. Send a start sequence
2. Send the I2C address of the slave with the R/W bit low (even address)
3. Send the internal register number you want to write to
4. Send the data byte
5. [Optionally, send any further data bytes]
6. Send the stop sequence.
As an example, you have an IC with the factory default ID or address of E0h.
Reading from the Slave
This is a little more complicated - but not too much more. Before reading data from the slave device, you must tell it which of its
internal addresses you want to read. So a read of the slave actually starts off by writing to it. This is the same as when you want
to write to it:
You send the start sequence, the I2C address of the slave with the R/W bit low and the internal register number you want to
write to. Now you send another start sequence (sometimes called a restart) and the I2C address again - this time with the read
bit set. You then read as many data bytes as you wish and terminate the transaction with a stop sequence.
1. Send a start sequence
2. Send 0xC0 ( I2C address example with the R/W bit low )
3. Send 0x01 (Internal address of the internal register ( example ))
4. Send a start sequence again (repeated start)
5. Send 0xC1 ( I2C address example with the R/W bit high )
6. Read data byte from the device
7. Send the stop sequence.
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The bit sequence will look like this:
Wait a moment
That's almost it for simple I2C communications, but there is one more complication. When the master is reading from the slave,
its the slave that places the data on the SDA line, but its the master that controls the clock. What if the slave is not ready to send
the data! With devices such as EEPROMs this is not a problem, but when the slave device is actually a microprocessor with
other things to do, it can be a problem. The microprocessor on the slave device will need to go to an interrupt routine, save its
working registers, find out what address the master wants to read from, get the data and place it in its transmission register. This
can take many uS to happen, meanwhile the master is blissfully sending out clock pulses on the SCL line that the slave cannot
respond to. The I2C protocol provides a solution to this: the slave is allowed to hold the SCL line low! This is called clock
stretching. When the slave gets the read command from the master it holds the clock line low. The microprocessor then gets the
requested data, places it in the transmission register and releases the clock line allowing the pull-up resistor to finally pull it high.
From the masters point of view, it will issue the first clock pulse of the read by making SCL high and then check to see if it really
has gone high. If its still low then its the slave that holding it low and the master should wait until it goes high before continuing.
Luckily the hardware I2C ports on most microprocessors will handle this automatically.
Sometimes however, the master I2C is just a collection of subroutines and there are a few implementations out there that
completely ignore clock stretching. They work with things like EEPROM's but not with microprocessor slaves that use clock
stretching. The result is that erroneous data is read from the slave. Beware!
Serielle EEPROMS
En af de interessante komponenter, der med fordel kan kobles til vores uC, er en EEPROM. Denne
er en hukommelse, der kan gemmes data i, uden at de forsvinder når spændingen fjernes.
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En EEPROM er en hukommelseskreds,
der kan kobles til en uC. Gemte data
”glemmes ikke” selv om spændingen
fjernes.
Her er vist en oversigt over EEPROM’s
til forskellige “bus-familier”.
Alle data er organiseret i 8 bit
Nogle enheder kan håndtere forskellige modes. fx Current adress read, Random read, eller
Sequential read.
Standard I2C protokollen for EEPROMS var designet til op til 16 Kbit memory. Dvs. 2 Kbyte a’ 8
bit.
Bit 0:
X = 1, Read
X = 0, Write
IC-Navn
24LC01B
24LC01
85C72
24LC02
85C82
24LC04
85C92
24LC08
24LC16B
AT24C164
AT24C32
AT24C64
AT24C128
/: Valle Thorø
størrelse
1 Kbit
8 byte page
Antal blokke
1 Blok
Op til 8 på bussen
2 Kbit
8 Bit page
4 Kbit
16 Byte page
8 Kbit
16 Byte page
16 KBit
16 Kbit
16 Byte page
32K Bit
32 Byte page
64 K Bit
32 Byte / page
128 Kbit
1 Blok
8
2 Blokke
A2 A1 X
4 Blokke
A2 X X
8
Extended ??
X X X Kun 1 device
8, A2, A1 A0
8 pr bus, A2, A1 A0
8 pr bus, A2, A1, A0
4, A0, A1
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256 Kbit
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4, A0, A1
24C16 kan adresseres som 1010 A10 A9 A8 R/W. Med de tre bit A10, A9 og A8 kan vælges blandt
8 enheder. ??
Her et forsøg på at tegne et flow for et program:
SPI, 3-wire, Microwire og 4-wire-busserne:
Fælles for disse busser, er, at de bruger en separat ledning til at vælge den chip, der ønskes kontakt
med.
Disse nævnte busser arbejder nogenlunde ens. De laves af forskellige firmaer, og har lidt forskellige
måder, de skal forbindes på og arbejder på.
Se evt. en sammenligning: http://www.coridium.us/ARMhelp/index.htm#page=HwSPIMicrowire.html
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SPI står for Serial Peripheral Interface. SPI-bussen bruger 4 wirer. Chip Select, Clock, og 2
dataledninger, en i hver sin retning.
Men man kan også støde på opsætninger, hvor den ene data-ledning er udeladt, - fx hvis der kun
skal læses fra en IC.
Og der findes IC-er til SPI-bussen, hvor data sendes og modtages på samme ledning. Den kan så
bare være kaldt ”Data”. Denne type kan kun arbejde i half-duplex, dvs. data i en retning ad gangen.
SPI 4 wire setup
SPI 3 wire setup.
http://elk.informatik.fh-augsburg.de/da/da-49/da-thoms-cc.pdf
SPI er skabt af Motorola i midt 1980’erne.
Nogle gange kaldes SPI-bussen også for 4-wire serial bus.
SPI bussen kan sammenlignes lidt med microwire bussen. Den bruger lignende signal-navne og
commando-protokol. Men den clock’er data ind og ud lidt anderledes. Data kan klockes med meget
højere frekvens end microwire. Op til 5 MHz!
I nyere microcontrollere kan der være indbygget en SPI-port!
Fra nettet:
The SPI bus specifies four logic signals:
SCLK:
MOSI; SIMO:
MISO; SOMI:
SS:
serial clock (output from master);
master output, slave input (output from master);
master input, slave output (output from slave);
slave select (active low, output from master).
Alternative naming conventions are also widely used:
SCK; CLK:
SDI; DI, DIN, SI:
SDO; DO, DOUT, SO:
/: Valle Thorø
serial clock (output from master)
serial data in; data in, serial in
serial data out; data out, serial out
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The SDI/SDO (DI/DO, SI/SO) convention requires that SDO on the master be connected to SDI on
the slave, and vice-versa. Chip select polarity is rarely active high, although some notations (such
as SS or CS instead of nSS or nCS) suggest otherwise.
SPI interfacen er command drevet.
For at læse data fra Memory,
vælger hosten eller masteren en
device, vha. chip-select, sender
READ kommando, sender
adressen af den byte, der ønskes
læst, og clocker så data ud af
device gennem SO pin.
( Seriel Out )
Ved afslutningen de-selecter
hosten igen kredsen.
Der kan være software forskelle
mellem fabrikater af SPI-ic’er.
http://www.eeherald.com/section/design-guide/esmod12.html
Fra Nettet
The 3-wire nomenclature is the general category of emcompassing the SPI and Microwire
busses. The Microwire is a subset of SPI with slightly different timing and data latching. This
last part tripped us up at work when we tried to access an SPI EEPROM with a PIC configured
for the Microwire data latching.
SPI
The Serial Peripheral Interface (SPI) is a synchronous serial bus developed by Motorola and
present on many of their microcontrollers.
The SPI bus consists of four signals: master out slave in (MOSI), master in slave out (MISO),
serial clock (SCK), and active-low slave select (/SS). As a multi-master/slave protocol,
communications between the master and selected slave use the unidirectional MISO and MOSI
lines, to achieve data rates over 1Mbps in full duplex mode. The data is clocked simultaneously
into the slave and master based on SCK pulses the master supplies. The SPI protocol allows
for four different clocking types, based on the polarity and phase of the SCK signal. It is
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important to ensure that these are compatible between master and slave.
In addition to the 1Mbps data rate, another advantage to SPI is if only one slave device is
used, the /SS line can be pulled low and the /SS signal does not have to be generated by the
master. (This capability is, however, dependent on the phase selection of the SCK.)
A disadvantage to SPI is the requirement to have separate /SS lines for each slave. Provided
that extra I/O pins are available, or extra board space for a demultiplexer IC, this is not a
problem. But for small, low-pin-count microcontrollers, a multi-slave SPI interface might not
be a viable solution.
For more detail on SPI, read David and Roee Kalinsky's "Beginner's Corner: Serial Peripheral Interface"
(February 2002).
Microwire
Microwire is a three-wire synchronous interface developed by National Semiconductor and
present on their COP8 processor family.
Similar to SPI, Microwire is a master/slave bus, with serial data out of the master (SO), and
serial data in to the master (SI), and signal clock (SK). These correspond to SPI's MOSI,
MISO, and SCK, respectively. There is also a chip select signal, which acts similarly to SPI's
/SS. A full-duplex bus, Microwire is capable of speeds of 625Kbps and faster (capacitance
permitting).
Microwire devices from National come with different protocols, based on their data needs.
Unlike SPI, which is based on an 8-bit byte, Microwire permits variable length data, and also
specifies a "continuous" bitstream mode.
Microwire has the same advantages and disadvantages as SPI with respect to multiple slaves,
which require multiple chip select lines. In some instances, an SPI device will work on a
Microwire bus, as will a Microwire device work on an SPI bus, although this must be reviewed
on a per-device basis.
Both SPI and Microwire are generally limited to on-board communications and traces of no
longer than 6 inches, although longer distances (up to 10 feet) can be achieved given proper
capacitance and lower bit rates.
http://www.embedded.com/design/connectivity/4023975/Serial-Protocols-Compared
SPI-Modes
The exchange itself has no pre-defined protocol.
This makes it ideal for data-streaming
applications. Data can be transferred at high
speed, often into the range of the tens of
megahertz. The flip side is that there is no
acknowledgment, no flow control, and the
master may not even be aware of the slave's
presence.
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The frame of the data exchange is described by two parameters, the clock polarity (CPOL) and the
clock phase (CPHA). This diagram shows the four possible states for these parameters and the
corresponding mode in SPI.
http://www.totalphase.com/support/kb/10045/
SPI-enheden indbygget i controllere kan
typisk konfigureres på 4 forskellige modes
http://elm-chan.org/docs/spi_e.html
The Serial Peripheral Interface Bus or SPI bus is a very loose standard for controlling
almost any digital electronics that accepts a clocked serial stream of bits. A nearly identical
standard called "Microwire" is a restricted subset of SPI.
SPI is cheap, in that it does not take up much space on an integrated circuit, and effectively
multiplies the pins, the expensive part of the IC. It can also be implemented in software with a
few standard IO pins of a microcontroller.
Many real digital systems have peripherals that need to exist, but need not be fast. The
advantage of a serial bus is that it minimizes the number of conductors, pins, and the size of
the package of an integrated circuit. This reduces the cost of making, assembling and testing
the electronics.
A serial peripheral bus is the most flexible choice when many different types of serial
peripherals must be present, and there is a single controller. It operates in full duplex (sending
and receiving at the same time), making it an excellent choice for some data transmission
systems.
In operation, there is a clock, a "data in", a "data out", and a "chip select" for each integrated
circuit that is to be controlled. Almost any serial digital device can be controlled with this
combination of signals.
SPI signals are named as follows:
SCLK - serial clock
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MISO - master input, slave output
MOSI - master output, slave input
CS - chip select (optional, usually inverted polarity)
Most often, data goes into an SPI peripheral when the clock goes low, and comes out when the
clock goes high. Usually, a peripheral is selected when chip select is low. Most devices have
outputs that become high impedance (switched-off) when the device is not selected. This
arrangement permits several devices to talk to a single input. Clock speeds range from several
thousand clocks per second (usually for software-based implementations), to several million
per second.
Most SPI implementations clock data out of the device as data is clocked in. Some devices use
that trait to implement an efficient, high-speed full-duplex data stream for applications such as
digital audio, digital signal processing, or full-duplex telecommunications channels.
On many devices, the "clocked-out" data is the data last used to program the device. Readback is a helpful built-in-self-test, often used for high-reliability systems such as avionics or
medical systems.
In practice, many devices have exceptions. Some read data as the clock goes up (leading
edge), others read as it goes down (falling edge). Writing is almost always on clock movement
that goes the opposite direction of reading. Some devices have two clocks, one to "capture" or
"display" data, and another to clock it into the device. In practice, many of these "capture
clocks" can be run from the chip select. Chip selects can be either selected high, or selected
low. Many devices are designed to be daisy-chained into long chains of identical devices.
SPI looks at first like a non-standard. However, many programmers that develop embedded
systems have a software module somewhere in their past that drives such a bus from a few
general-purpose I/O pins, often with the ability to run different clock polarities, select
polarities and clock edges for different devices.
Fra: http://www.coridium.us/ARMhelp/index.htm#page=HwSPIMicrowire.html
SPI-Bussen og 3-wire sammenlignet:
De to busser, 3-wire og SPI er næsten lig hinanden. Her en sammenligning mellem de to:
http://www.maxim-ic.com/appnotes.cfm/an_pk/169
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Her en skitse af signalerne på
ledningerne.
For mere se:
http://www.mct.de/faq/spi.html
http://www.rpi.edu/dept/ecse/mps/Coding_SPI_sw.pdf
http://www.mikroe.com/en/books/8051book/ch4/ ( for SPI indbygget i en uC )
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Microwire:
National Semiconductors Microwire er det same som SPI. Sometider kaldes SPI for "four wire"
serial bus.
Her følger en del afsnit, gaflet forskellige steder på nettet.
MICROWIRE is a 3Mbps [full-duplex] serial 3-wire interface standard defined by National Semiconductor. The
MICROWIRE protocol is essentially a subset of the SPI interface, CPOL = 0 and CPHA = 0. Microwire is a serial I/O
port on microcontrollers, so the Microwire bus will also be found on EEPROMs and other Peripheral chips.
Microwire is essentially a predecessor of SPI. It's a strict subset: half duplex, and using SPI mode 0. Microwire-Plus
supports other SPI modes. Microwire chips tend to need slower clock rates than newer SPI versions; perhaps 2 MHz vs.
20 MHz. Some Microwire chips also support a 3-Wire mode see below, which fits neatly with the restriction to half
duplex.
Das, von National Semiconductor entwickelte Microwire ist zu SPI kompatibel, definiert jedoch
(ahnlich SMBus für I2C) striktere Regeln fur die Hard- und Softwareteile des Busses. Damit ¨
konnen Microwiregeräte praktisch an jedem SPI Master betrieben werden. ¨
Der originale Microwire Standard ist kompatibel zum SPI mode 1. Viele altere SPI Geräte
implementieren aber nur den SPI mode 0, der genau andersherum funktioniert. Microwire/Plus
behebt dieses Problem, indem ein SKSEL Bit (shift clock select) eingefuhrt wird, um zwischen den
SPI - modes 0 und 1 umzuschalten.
http://elk.informatik.fh-augsburg.de/da/da-49/da-thoms-cc.pdf
Det er en af de ældste serielle busser. Populær ved høj volumen i lang tid. Supporterer nogle af de
billigste serielle hukommelseskredse. Er hurtig nok til mange applikationer, men supporterer ikke så
mange kredse
Kræver flere portpins end I2C
Interface speed er max 1 MHz. Clock’er data ind og ud på samme clock flanke. En lignende bus,
SPI clock’er data ind og ud på modsatte clock-flanker, og har højere hastighed.
Selvom Microwire bussen har nogle fordele, er det den første, der vil forsvinde. ( www.xicor.com)
Maxim 3-wire
The Maxim 3-wire interface is found on the DS1620 and some other ICs from Maxim The data
flow to and from the DS1620 is multiplexed on only one pin (DQ) while SPI needs two
separate signals (MOSI, MISO).
One variant of SPI uses single bidirectional data line (slave out/slave in, called SISO) instead
of two unidirectional ones (MOSI and MISO). Clearly, this variant is restricted to a half duplex
mode. It tends to be used for lower performance parts, such as small EEPROMs used only
during system startup and certain sensors, and Microwire. As of this writing, few SPI master
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controllers support this mode; although it can often be easily bit-banged in software.
When someone says a part supports SPI or Microwire, you can normally assume that means
the four-wire version.
However, when someone talks about a part supporting a 3-wire serial bus you should always
find out what it means: standard 4-wire SPI, without the chip select pin from that count, since
most buses use chip selects but only three wires carry "real" signals; (More, sometimes with
an unshared SPI bus segment the device's chip select will be hard-wired as "always selected".)
"real" 3-wire SPI; or even a RS232 cable with RXD, TXD, and shield/ground, or an applicationspecific signaling scheme.
Fra: http://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus
Andre firmaer kalder bare deres signal-ledninger for Data, Clock og CS ( Chip Select )
Sammenkobling af forskellige busser?
Måske sådan kan 4 og 3-wire kobles
sammen ??
http://www.totalphase.com/support/kb/10059/
Sammenkobling af I2C og SPI Bus
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Konverter fra I2C til 485:
http://xj900diversion.free.fr/bus/I2C%20-%20RS-485%20adapter.htm
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1-wire Bus, MicroLAN,
1-wire bussen er fra Dallas Semiconductor / Maxim
Dallas / Maxim 1-wire bussen bruger en enkel datalinje til at sende og modtage data. Derfor kaldes
den 1-Wire.
Hver 1-Wire enhed skal også forbindes til fælles ground, og optional til en power supply. Hvis
powersupply udelades, kan 1-wire enheden strømfødes ”parasitisk” fra dataledningen.
1-wire bussen er normalt holdt høj, med en 4,7 K modstand til Ucc. Når der sendes data, trækkes
bussen kortvarigt lav i henhold til bittene.
Busprotokollen arbejder med et antal definerede signaltyper. En reset puls, ”presence puls”, Write 0,
Write 1, Read 0, Read 1.
Hvert signal har timing parameter som skal strengt overholdes. Derfor er det vigtigt, at systemet er i
stand til at generere akkurate timeslots.
For fuldstændig oversigt over 1-Wire signalling refereres til dokumentation på Dallas/Maxim’s
hjemmeside.
Data sendes ved at trække data linien lav. Kortere end 15uS er et “1”, længere end 60uS = ”0”.
Kaldes for q-PWM Code Bus System
Kredse:
Der finds et antal IC-kredse, der anvender 1-Wire: Fx:
DS18x20, Temperaturcensor I TO92 hus. DS18S20 giver 9 bit / 0,5 grader C opløsning, og
DS18B20 giver op til 12 bits opløsning, 0,0625 grader. Begge med tollerencer inden for 0,5 grader.
DS 2401, Bruges til serial nummer, eller ID-chip !. Fås i SMD eller TO92 hus ! IC-en sender en 8
bit familiekode, ( Type of device ), dernæst 48 bit unik kode, og 8 bit CRC, Cyclic Redundancy
Check
Dvs at den serielle nummerkreds er programmeret med en ud af 248 koder, eller 2,8E14 koder !
Den kendes også fx som iBUTTON
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DS 1920 Temperaturcensor ! og IC til adgangskontrol.
Se: http://en.wikipedia.org/wiki/1-Wire
Bonus info:
Af følgende oversigt fremgår, at der findes et større antal bussystemer.
1-Wire
I2C*
SMBus™
SPI™
MicroWire/PLUS™
M-Bus
(EN1434)
CAN
(ISO11898)
LIN Bus
Network
Concept
single
master,
multiple
slaves
multiple
masters,
multiple
slaves
multiple
masters,
multiple
slaves
single
master,
multiple
slaves
single master,
multiple slaves
single
master,
multiple
slaves
multiple
masters,
multiple
slaves
single
master,
multiple
slaves
Number of
Signal Lines
1 (IO)
2, (SCL,
SDA)
2, (SMBCLK, 4, (CS\, SI,
SMBDAT)
SO, SCK)
4, (CS\, DI, DO, SK)
2 (CAN_H,
2 (lines can
CAN_L,
be swapped)
terminated)
Optional
signals
N/A
N/A
SMBSUS#,
N/A
SMBALERT#
N/A
N/A
2nd GND,
Power,
Shield
Limited by
max. 400pF
bus
capacitance
requirement
Limited by
max. 400pF
bus
capacitance
requirement
N/A (circuit board
level)
Max. 350m
per segment
of max. 250
slaves; max.
180nF
40m @1M
Up to 40m,
bps1000m @
max. 10nF
50k bps
total load
(example)
open drain,
resistive or
active master
pull-up
open drain,
resistive or
Push-pull
active master with tristate
pull-up
Push-pull with
tristate
Differential
M to S:
open
voltage drive
drain/source
S to M:
or open
current load
coll./emitter
Up to 300
m (with
Network Size suitable
master
circuit)
Network
Interface
open drain,
resistive or
active
master
pull-up
Network
Voltage
From 2.8 to
From 1.8 to
6.0 V,
5.5V, device
device
specific
specific
Logic
Thresholds
Vary with
network
voltage
/: Valle Thorø
2.7V to 5.5V
Fixed level:
>1.5V, >3.0 V
<0.8V, >2.1V
VDD-related
level: <30%,
N/A (circuit
board level)
1 (LIN)
N/A
open drain,
resistive
master pullup
From 1.8V to
From 1.8V to 5.5V,
5.5V, device
device specific
specific
~40V
VDD-VD
(diode drop); 8 to 18V
~4.5V max.
VDD-related
level: <20%
(30%), >70%
of VDD
Master to
slave: 24V,
36V
nominalSlave
Differential:
<50mV
(recessive),
>1.5V
Fixed level: <0.8V,
>2.0V; VDD-related
level: <20% (30%),
>70% (80%) of VDD
VDD-related
level: <20%,
>80% of VDD
(driver
Side 34 af 40
Busser

>70% of VDD
MS bit first
plus
LS bit first,
Transmission
Acknowledge
half-duplex
bit, halfduplex
(inconsistent) (inconsistent)
MS bit first
plus
MS bit first,
Acknowledge
full-duplex
bit, halfduplex
Address
Format
56 bits
7 bits, (10 bits
defined but
not
implemented)
Network
Inventory
Automatic,
supports
dynamic
topology
change
N/A; slave
addresses
hard-coded in
firmware
Gross Data
Rate
Standard:
~0 to 16.3k
bps
Overdrive:
~0 to 142k
bps)
Standard: ~0
to 100k bps;
Fast: ~0 to
10k to 100k
400k bps;
bps
High-Speed:
~0 to 3.4M
bps
Standard:
~ 5.4ms
Overdrive:
Access Time
~0.6ms (at
maximum
speed)
Standard:
~95µsFast:
~23µs(at
maximum
speed)
to master:
<1.5mA,
>11mA
(dominant);
driver
specification
MS bit first, fullduplex
LS bit first,
half-duplex,
MS bit first,
acknowledge half-duplex
response
8 bits
(primary
address), 64
bits
(secondary
address)
spec.)<40%,
>60% of VDD
(receiver
spec.)
LS bit first,
half-duplex
Message
identifier 11
bits (standard
format), 29
bits
(extended
format)
Message
identifier 8
bits,
including 2
parity bits
N/A; slave select
(CS\) hard-coded in Automatic
firmware
N/A;
messagebased
protocol, not
address
based
N/A;
messagebased
protocol, not
address
based
~0 to ~5 M bps
(device specific)
300, 2400,
9600 bps
~0 to 1M bps
~1k to ~20k
bps
N/A
N/A
Primary
address,
2400 bps:
13.75ms
(short frame),
27.5ms (long
frame)
At 1M bps
19µs
(standard) or
39µs
(extended)
from start of
frame to 1st
data bit
At 20k bps
1.7ms from
start of
frame to 1st
data bit
7 bits, (10
bits defined
N/A
but not
implemented)
N/A
ARP,
Address
Resolution
Protocol
(Rev. 2.0
only)
N/A; slave
select (CS\)
hard-coded
in firmware
~0 to ~10 M
bps (device
specific)
~95µs @
100k bps
Version
11/11-2015
Data
Protection
8-bit and
N/A
16-bit CRC
PEC Packet
Error Code
N/A
(Rev.1.1, 2.0)
N/A
Even parity,
check sum,
frames
15-bit CRC,
frames,
Check sum,
frame
frames
acknowledge
Collision
Detection
Yes,
through
nonmatching
CRC
Yes (Rev. 2.0
N/A
only)
N/A
Yes
("medium"
and "strong"
collisions)
Yes:
CSMA/CD
Yes, through
check sum
VDD only
Parasitic
and/or local
supply
VDD only,
local or
remote
source
Parasitic
only
Yes (multimaster
operation
only)
Parasitic
(typical),
Slave supply
VDD only
VDD
(exception)
VDD only
VDD only
http://www.maxim-ic.com/appnotes.cfm/appnote_number/3438
http://www.bipom.com/applications/micro_interfacing.pdf
Bonus info: Marts 2014:
SPI-Allgemeines
/: Valle Thorø
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Beim SPI-Bus (Serial Peripheral Interface) handelt es sich um einen synchronen 3-Draht Bus mit einer
zusätzlichen Steuerleitung (/SS) Er wurde von Motorola Anfang 1989 entwickelt und bietet einen volldupplex
Datentransfer. Spezifiziert wurde er damals für 3 MBits/s. Heute gibt es für diesen Bus Bausteine mit bis zu 33
Mbits/s. Für jedes /SS-Signal wird ein eigener Portpin am Master benötigt. Ist das /SS-Signal am Slave auf High,
sind die anderen Eingänge des Slave im Tri-State. Der Master selbst benötigt keinen /SS-Pin.
Die Übertragung mit einen SPI-Bus erfolgt folgendermaßen:
1. Der Master setzt den /SS-Pin auf Low. Dies wird mit Hilfe von Software realisiert.
2. Danach wird ein Wert in das Übertragungsregister (SPDAT) geschrieben. Durch das Einschreiben wird die
Übertragung automatisch gestartet und das zu sendende Byte wird über den Portpin MOSI seriell
herausgeschoben synchron zum SPICLK.
Gleichzeitig werden acht Bits über den Portpin MISO empfangen. Somit ist jeder Sendevorgang grundsätzlich
mit einem Empfangsvorgang automatisch verbunden. Will der Master nur einen Wert senden, so ist die
Empfangsinformation irrelevant. Der Slave-Baustein sendet keine Quittung zurück. Es können nun ein weitere
Bytes ohne Zeitverzögerung in gleicher Weise gesendet und empfangen werden.
3. Soll nur ein Wert aus dem Slave gelesen werden, muss dennoch ein Dummywert gesendet werden.
4. Die Übertragung an den Slave wird gestoppt, indem kein weiterer Wert mehr in das SPDAT geschrieben und
das /SS-Pin auf High gelegt wird. Erst danach kann der Master einen anderen Slave ansprechen.
5. Die Verwendung des SPI-Buses ist softwaremäßig einfacher, als die des I²C-Busses, da kein Adressfeld mit
gesendet und ausgewertet werden muss.
Mittels dem Signal /SS wird der Slave aktiviert. Sind mehrere Slaves am SPI-Bus angeschlossen, wird für jeden
Slave ein weiteres /SSx-Signal benötigt. Mit der MOSI-Leitung werden die Daten seriell vom Master zum Slave
gesendet. Mit der MISO-Leitung werden die Daten vom Slave empfangen. Die SPICLK-Leitung sorgt für die
Taktvorgabe vom Master.
Vorteile des SPI gegenüber dem I²C-Bus:
Schneller Datentransfer
Bidirektionale Datentransfer
Einfaches Protokollhandling
Jeder Slave kann mit der maximalen Taktfrequenz betrieben werden, da jeweils nur ein Slave aktiv am SPI-Bus
ist. Beim I²C-Bus bestimmt der langsamste Teilnehmer die Taktfrequenz.
Nachteile des SPI gegenüber dem I²C-Bus:
Für jeden Slave wird eine zusätzliche Steuerleitung (/SS) benötigt.
Es kann keine Überprüfung stattfinden, ob der Slave angeschlossen ist, bzw. die Daten
empfangen hat.
/: Valle Thorø
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11/11-2015
Bilag:
I2C-Assembler-program til 8051-familien
For at kommunikere med en IIC-chip, kan man klare sig med nogle få standard-subrutiner, også
kaldet primitives. De er ret simple, - se fx: http://www.8051projects.net/i2c-twi-tutorial/8051-i2cimplementation.php
Derudover nogle, hvor der er indbygget fejl-detektering, der kan tjekke, om fx en adresseret IC ikke
er sat i sin sokkel. Se disse senere:
Primitiver: Eller subrutiner, der kan bruges til at
kommunikere med en I2C-kreds kan fx have
I2C_start:
disse navne:
I2C_stop:
I2C_sendbyte:
I2C_modtag:
I2C_ACK: ( Modtaget )
I2C_NACK: ( end of transmission )
Her følger en mere udførlig gennemgang af subrutinerne:
; ------------------------------; Send startsignal. SDA og SCL gøres lave, og Cy sættes !
; Er bussen optaget, returneres med C = 1.
I2C_start:
Setb SDA
Setb SCL
JNB SDA, I2C_START1
JNB SCL, I2C_start1
Clr SDA
CLR SCL
CLR C
JMP I2C_START2
I2C_start1:
Setb C
I2C_start2:
RET
; Tjeck for bus ikke optaget, optaget hvis lav !
; -”–
; begge linier gøres lave
; og Cy flaget også lav
; ------------------------/*
/: Valle Thorø
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Send stopsignal:
Gør SDA kortvarig lav, mens SCL gøres høj.
SCL forventet lav ved start. Slut med SCL og SDA høj.
*/
I2C_stop:
Clr SDA
NOP
Setb SCL
NOP
Setb SDA
RET
;
; -------------------------------------/*
Send Byte:
Rutinen kaldes med data I A-registeret. Efter at en byte er sendt, tjekker rutinen for om der
modtages en ACK. ACK-værdien returneres i CY. Cy = 0 => ??, Cy = 1 => ??.
Send en byte ud på I2C-bussern, MSB først.
SCL og SDA forventet lav ved start. Slut med SCL lav
Data, der skal sendes i reg A ved start.
Returnerer med CY sat for at indikere en not acknowledge fra slaven.
Ødelægger indholdet i A efter byte er sendt.
*/
I2C_sendbyte:
Push B
Mov b, #8
I2C_sendbyte1:
RCL A
Mov SDA, C
Setb SCL
NOP
Clr SCL
DJNZ b, I2C_sendbyte1
; 8 bit er nu sendt
; modtag Ack fra slave
setb SDA
Setb Scl
Nop
Mov C, SDA
Clr SCL
POP b
RET
; Roter A ud i Cy
; C til SDA-bus
; clock kortvarig høj
; vent på at slave sender Ack
; læs Ack-bit til Carry-bit
; ----------------------------------
/: Valle Thorø
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/*
Modtage byte
B gemmes, modtagne data gemmes i ACC. Først modtagne bit = MSB.
SCL forventet lav ved start. Slut med SLC lav
Returnerer den modtagne byte i A
*/
I2C_modtag:
Setb SDA
Push b
Mov B, #8
; indstil tæller til 8 bit.
I2C_modtag1:
Setb SCL
; clock høj
nop
Mov C, SDA
RCL A
DJNZ b, I2C_modtag1
; igen i alt 8 gg.
Pop b
RET
; -----------------------------/*
Send ACK. ( ala ?? ”Modtaget” )
Sender ACKNOWLEDGE bit ud ( low )
SCL forventet lav ved start. Slut med SCL og SDA lave.
*/
I2C_ACK:
Clr SDA
NOP
Setb SCL
NOP
Clr SCL
NOP
RET
; -----------------------------/*
Send Not ACK.
Send en NOT ACKNOWLEDGE bit ud ( Høj )
SLC forventet lav ved start. Slut med SCL lav og SDA høj.
*/
I2C_NACK: ( Not Acknowledge (End of Transmission) )
Setb SDA
NOP
Setb SCL
;
Klock kortvarig høj
NOP
CLR SCL
/: Valle Thorø
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RET
; ---------------------------------Se for yderligere oplysninger:
http://www.esacademy.com/en/library/technical-articles-and-documents/miscellaneous/i2c-bus.html
http://www.robot-electronics.co.uk/acatalog/I2C_Tutorial.html ( Med C-kode )
http://www.totalphase.com/support/kb/10039/
http://www.eeherald.com/section/design-guide/esmod11.html
http://www.best-microcontroller-projects.com/i2c-tutorial.html
http://www.i2c-bus.org/i2c-bus/
http://www.i2c-bus.org/i2c-primer/
I2C-bus specification and user manual:
http://www.nxp.com/documents/user_manual/UM10204.pdf
I2C på 8051 både ASM og C: http://www.8051projects.net/i2c-twi-tutorial/8051-i2c-implementation.php
Flowchart: http://www.holtek.com.tw/english/tech/appnote/uc/pdf/ha0149e.pdf
/: Valle Thorø
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