POET Technologies Enabling the Future
POET Technologies Enabling the Future Corporate Presentation January 2015 Safe Harbor The following presentation, other than statements of historical fact, may include certain “forward-looking statements” within the meaning of the United States Private Litigation Reform Act of 1995 and applicable Canadian securities laws. These forward looking statements are made under the “Safe Harbor” provisions of the aforesaid act and laws. All statements regarding future plans and objectives are forward-looking statements. Words such as “expect”, “anticipate”, “estimate”, “future plans”, “may”, “will”, ”should”, “intend”, “believe”, “opportunities”, and other similar expressions are forward-looking statements. Forward-looking statements are subject to risks, uncertainties, assumptions and are not guarantees of future results, but rather reflect current views with respect to future events. Important factors that could cause actual results to differ materially from those expressed or implied in the forward looking statements include risks and factors disclosed under the heading “Risk Factors” in the public documents filed from time to time with the System for Electronic Document Analysis and Retrieval (“SEDAR”). Readers should not place undue reliance on any forward-looking statements. We disclaim any obligation to update or revise any forward looking statements, except as required by law to reflect any change in expectations, events, conditions or circumstances on which any of the forward looking statements are based, or that may affect the likelihood that actual results will differ from those set forth in the forward-looking statements. © 2014 POET Technologies Inc. – Corporate Presentation January 2015 2 Corporate Introduction POET Technologies has created a revolutionary semiconductor technology capable of replacing current siliconbased IC devices while delivering up to 90% power savings and dramatic performance gains in like applications. © 2014 POET Technologies Inc. – Corporate Presentation January 2015 3 Company Overview Who Is POET? § POET Technologies, Inc., is a semiconductor technology development company § Full and/or Exclusive IP Ownership ‒ Has been granted 34 patents with 7 additional patents pending ‒ Continues to drive IP pipeline § Currently listed on the TSX Venture Exchange and OTC QX (US) § Fully SEC compliant (20-F) § Lab facilities at Storrs Connecticut. HQ in Toronto, Canada Background & Objectives § POET provides revolutionary and disruptive III-V semiconductor process and device intellectual property (IP) § Vs. existing technologies, POET enables: þ Increased performance þ Lower power consumption þ Novel devices with wider range of functionality in integrated solutions þ Lower system cost through device consolidation and power reduction POET will license process IP and generate revenue from fabs and customers © 2014 POET Technologies Inc. – Corporate Presentation January 2015 4 Management Team Peter Copetti Exec. Co-Chairman & Interim CEO § Chief architect and strategist of POET transformation § Leading POET’s resurgence and monetization activities § Capital markets expertise § 35 years of semiconductor industry experience with deep knowledge of the technology and operations § Most recently CEO of GlobalFoundries (Multi-Billions $US Revenues) § Strategic direction advisor to the CEO Ajit Manocha Exec. Co-Chairman Dr. Geoffrey Taylor Chief Scientist § Technology and IP generation pioneer and world renowned expert in GaAs and inventor of the POET platform § POET technology development for over 20 years Daniel DeSimone § 30+ years of semiconductor development and fabrication experience § Responsible for process IP product development Stephane Gagnon § 20+ years of semiconductor and telecom management experience § Responsible for overall operations and business development Chief Technology Officer Chief Operating Officer © 2014 POET Technologies Inc. – Corporate Presentation January 2015 5 Dr. Geoff Taylor Chief Scientist Biography § Professor of Electrical & Computer Engineering at the University of Connecticut § Co-Founder & Chief Scientist of POET Technologies Inc. § Has dedicated more than 25 years towards the development of a gallium arsenide (GaAs) semiconductor chip • Began research on the GaAs semiconductor chip while working at Bell Laboratories in New Jersey § Background in the areas of materials, devices and circuits for microelectronics § 34+ patents issued and 150+ journal papers published § B.Sc, Electrical Engineering, Queens University (1966) M.A.Sc, Electrical Engineering, University of Toronto (1968) Ph.D, Electrical Engineering, University of Toronto (1972) © 2014 POET Technologies Inc. – Corporate Presentation January 2015 6 Total Addressable Markets Global Electronic Component and Semiconductor Industry § § Specific Market TAM Examples Global market is expected to reach $628 billion, according to MarketLine Integrated Circuit semiconductors is the leading market segment with 54% of overall market § Cellphone ICs ($119 billion 2016F) § Standard PC and Tablets ICs ($102 billion 2016F) § MOS Memories: DRAM, SRAM and Flash ($89.3 billion 2016F) § General Purpose Logic ($108 billion 2016F) § Sensors and Actuators ($13 billion 2016F) PC & Cellphone IC Markets ($Billions) $120 $119 $100 $102 Tablet & Other PC ICs! $80 $60 Cellp hone IC s! $40 Standard PC ICs! Source: IC Insights $20 $0 2008 2009 2010 2011 2012 2013E 2014E 2015E 2016E Source: IC Insight Example of POET’s addressable market: PC & Cellphone IC market is growing to over $220 billion by 2016 © 2014 POET Technologies Inc. – Corporate Presentation January 2015 7 The Problem Silicon node migration is hitting physical barriers: § Silicon clock speed is flattening out § Power is flattening out with silicon § Performance / clock is flattening with silicon § Chip tapeout “Non Recurring Engineering” (NRE) costs are escalating geometrically with node Source: Herb Sutter, “The Free Lunch Is Over: A Fundamental Turn Toward Concurrency in Software” , Dr. Dobb’s Journal, 30(3), March 2005 (graph updated in 2009) © 2014 POET Technologies Inc. – Corporate Presentation January 2015 8 The Solution Change the Semiconductor Material § III-V transistors perform at least 5X better than Si based transistors at same node. Our projection is that logic performance in our technology should be equivalent to a 3 to 4 node jump in Si technology § III-V transistors also make much better analog circuitry which results in far superior mixed signal performance that is key to today’s SoCs § III-V materials make for excellent photonic devices Plus INTEGRATE Novel and Disruptive Capabilities § New active and passive optical devices to overcome on- and off-chip interconnect limitations of current Silicon CMOS solutions § Novel OE bipolar transistor and thyristor action without stored charge enables very high speeds PLUS act as photo detectors and emitters § New applications made possible by novel devices and integration § Optoelectronic functions implemented as co-packaged discrete devices replaced with single integrated device POET will enable integration at lower manufacturing costs © 2014 POET Technologies Inc. – Corporate Presentation January 2015 9 Semiconductor Industry Value Chain § Investment costs to keep up with semiconductor performance demand are increasingly high, and few Fab vendors can afford to keep up ‒ The integrated model is prohibitively high in today’s market Raw Materials Semiconductor Design Fabless Design TCAD Semiconductor Manufacturing Foundry Packaging Assembly & Testing Outsourced Assembly & Testing End Products OEMs Software allowing foundries to read design “recipes” POET can make use of the existing semiconductor manufacturing infrastructure © 2014 POET Technologies Inc. – Corporate Presentation January 2015 10 Inventions and Process IP POET - Planar Opto-Electronic Technology PET - Electrical only Technology § Extremely low power -- 4 nodes ahead of Silicon CMOS - PET & POET offer 0.3-0.5V operation vs 0.8V in Silicon CMOS § High performance applications – Up to 10x faster than current technologies POET Applications Digital Mixed mode Analog High voltage Optical § Multiple optical colors at rates of up to 50 Gbps per color Main Inventions – Never before realized in GaAs § First GaAs process technology to support integrated HFETs and HBTs (complementary logic) - New GaAs p and n HFET devices PET Applications Digital Mixed signal Analog - New GaAs p and n HBT devices § Supports concurrent fabrication of fully integrated electrical and optical circuit components - New GaAs Optical Thyristor device © 2014 POET Technologies Inc. – Corporate Presentation January 2015 11 Process Characteristics § POET (Planar Opto-Electronic Technology) is a novel III-V compound semiconductor process technology which utilizes InGaAs modulation doped Quantum Wells § First GaAs process technology to support complementary HFETs enabling significant static power savings compared to bipolar or active load compound semiconductor processes in use today § POET supports concurrent fabrication of a full range of highly efficient electrical and optical circuit components on a single die in a single process § Provides density similar to traditional Silicon CMOS § Provides dramatically reduced switching and non-switching power consumption compared to silicon technologies § Compatible with existing and planned package technology § Standard wafer epitaxy techniques and equipment § Standard lithography-based fabrication techniques and equipment § Provides traditional GaAs compound semiconductor electrical and optical performance capabilities § Supports fabrication of vertical and horizontal laser cavities © 2014 POET Technologies Inc. – Corporate Presentation January 2015 12 Value Proposition for Foundry Partner § Increase serviceable addressable markets (SAM) by offering - Speed and power upgrades for high speed digital offering - Photonics - Analog, Mixed Signals, Digital and optical integration capabilities - Universal memory cell (NVRAM, DRAM and SRAM) - Radiation Hardness - IGBT implementation for power applications/epitaxy in GaN § PET and POET process will match power/performance roadmap 3-4 node sizes ahead of Silicon CMOS - Extends Moore’s laws for foundries at much lower R&D and new investments costs - Lowers tapeout costs for fabless customers (see comparisons on slides 4 & 5) § Roadmap to integration of QUBIT blocks with conventional logic for Quantum Computing future application © 2014 POET Technologies Inc. – Corporate Presentation January 2015 13 Value Proposition for Datacenter Key Value Proposition § Significant server farm computational efficiency savings § True acceleration of single-thread computing at higher clock frequencies with lower power § Novel system partitioning, reducing electrical noise and power, utilizing chip to chip optical interconnect capable of 50 gbps per I/O (DWDM capable) POET enables on-chip coexistence of analog, digital, optical, and mixed-signal functions § Full on-device optical circuit capability, same-die same PIC (Photonic Integrated Circuit) capable process § Denser and lower noise designs are now possible using multi-color optical generation and global distribution of signals (e.g. clocks) § Lower operating voltage provides reduced power even at higher clock rates § Advanced optical capabilities, novel system interconnect via chip to chip optical, onchip and inter-chip switching fabric, optical computing are all possible with POET © 2014 POET Technologies Inc. – Corporate Presentation January 2015 14 Universal Memory Cell Memory architecture simplification of datacenter representing huge costs savings § POET supports a high speed, very high density thyristor-based universal memory cell § A single memory array can be operated as an SRAM, a DRAM, or NVRAM depending on controller configuration § NVRAM capability is phase-change type so no write-based device reliability issues like NAND flash § Can eliminate need for dedicated NVRAM for system backup and recovery since all embedded memories already have NVRAM capability § Density comparable to leading edge DRAM, and much higher than existing SRAM, NAND flash, NOR flash, or PCRAM technologies § Wide band gap material provides much higher noise immunity than Silicon-based technologies (several orders of magnitude improvement in soft error rates) © 2014 POET Technologies Inc. – Corporate Presentation January 2015 15 Application Examples vs. POET Capabilities Processors and SoCs § High Performance and Power step function § Low voltage operation è 0.3-0.5V § Analog and Mixed signal integration of arbitrary functions § CCD imaging, visible and IR § Applicable at all geometry levels from 3u to sub 28nm § TJ solar cell integrated with power control for all mobile systems Analog and Digital Optical Applications - Data Centers Servers Optical Components § Enabling microprocessor design at > 20GHz § Memory structures for NVRAM, SRAM and DRAM § Enabling Opto-Electronic designs on the same die § § § § VCSELs, 2D VCSEL arrays with integrated drivers High speed tunable lasers with integrated drivers TW detectors, SOA’s, modulators with electronics 3D Packaging electrical and optical © 2014 POET Technologies Inc. – Corporate Presentation January 2015 16 Manageable adoption for Industry Partners Fabless Design TCAD Foundry Design § Industry standard design tool flows § Addresses multiple process nodes § Low adoption cost Manufacturing and Testing § Supports existing manufacturing and testing infrastructure Outsourced Assembly & Testing § Employs all existing test on wafers techniques § Supports existing Silicon CMOS post fabrication procedures Performance and Integration OEMs § Up to 90% solution power savings versus existing technologies § Low core voltage operations possible down to 300mV § Supports electrical devices switching at over 500 GHz © 2014 POET Technologies Inc. – Corporate Presentation January 2015 17 Monetization Strategy Market Leaders NRE § Industry leaders in specific markets to buy exclusivity rights - Lock in POET IP keeping their competition out from using POET IP Direct Foundry NRE § Paid by foundries for POET to transfer and enable their foundry with PET/POET flow § Replaces R&D $$$ they would have spent on developing this capability in-house Foundry Design KIT – Flow-through NRE Royalties § Percentage of the POET foundry design kit revenue from foundries that develop libraries and specific design kits targeting the POET process that they will sell to their customers Semiconductor Chip Sales Royalties § Royalties on future semiconductor chip sale POET enabled from the foundry flow Initial NRE revenues expected to start in 2015 § End customer NRE, Foundry NREs, or a combination thereof © 2014 POET Technologies Inc. – Corporate Presentation January 2015 18 Synopsys TCAD and Enablement POET Process Design Kit (PDK) Development § POET and Synopsys are collaborating on the deployment of Sentaurus TCAD for the PDK project § Synopsys Sentaurus Process and Device TCAD software is used to accelerate development of a POET PDK for technology transfers to potential manufacturing partners • Process parameters and device design are optimized for manufacturability and performance • Calibration to measured structures ensures and verifies quality and accuracy of the technology description minimizing process transfer qualification time POET PDK Development § TCAD is also used to provide a pre-fabrication PDK suitable for design exploration § Allows early stage exploration for “System on a Chip” (SoC) and optical interconnect architectures leveraging unique functionality and performance of novel POET/PET technologies © 2014 POET Technologies Inc. – Corporate Presentation January 2015 19 Achieved Technical Milestones Milestone! Date! Technical Achievement! Definitions! Q2-11! Integrated Pulsed Laser" General purpose laser for on-chip use." Q2-11! p and n channel Complementary Heterostructure Field Effect Transistor Validation1" High performance, power efficient transistors. World’s first complementary GaAs HFETs." Q4-12! Continuous Wave Vertical Cavity Surface Emitting Laser Demonstration" High density laser design for surface-emitting applications (e.g. chip-to-chip in stacked-die array)." Q1-13! n-channel and p-channel Complementary Heterostructure Field Effect Transistor Radio Frequency Validation1 Demonstrating radio frequency and microwave performance of revolutionary complementary HFETs." Q1-14! 3/4 Terminal Switching Laser Demonstration" High quality pulsed laser type for critical signal propagation (e.g. clocks, optical line signaling)." Q2-13! Complementary Heterostructure Field Effect Transistorbased Inverter/Oscillator Demonstration" Complementary HFET-based ring oscillator (standard circuit configuration used to demonstrate process performance)." Q1-14! Optical Thyristor-based Infrared Detector Array Fabrication and Validation1" An array of optical thyristors configured as infrared detectors." Q3-14! Demonstration of 100 nm or below PET n- and pchannel device" Demonstration of p and n type HFETs and BJTs at sub-100 nm feature size." Performance optimization phase on-going." Q1-14! POET TDK (Technical Design Kit) Documentation" Full POET platform TDK documentation release." Note 1: Milestones noted above were accomplished with a 3rd party fab partner, an international defense services company that is a global leader in military electronic systems design, development, manufacturing and integration. The 3rd party partner has world-class GaAs research facilities and has numerous PhD researchers. POET’s partnership has successfully reproduced the POET technology as published, by producing and testing the critical electrical elements of POET Platform sub-process steps for transistors. © 2014 POET Technologies Inc. – Corporate Presentation January 2015 20 Future Technical Milestones and 2015 Roadmap Milestone Timeframe* Technical Milestone Defini4ons PET Founda+on PDK (Process Design Kit) targe+ng 40nm (V 1.0) Design rules and parameters library models for PET process. Devices include complementary HFET and HBT transistor and a thyristor with both op+cal and electrical opera+on. 3rd Party Foundry 40/100nm transfer Bring up cri+cal layers manufacturing capability in external foundry. Accelerates comple+on of development and op+miza+on learning cycles on 100 and 40nm structures. Also enables more complex test structures. Q1-‐15 Electrical 100nm ring oscillator Demonstra+on vehicle for high speed performance and power at 100nm process node. Reference standard to compare to Silicon CMOS. Q1-‐15 50 GHz VCSEL 50 GHz DWDM (dense wavelength division mul+plexing) ver+cal cavity laser device Q1-‐15 Jan-‐2015 Milestone Timeframe* 2015 Capability Development! Roadmap Definitions! PET PDK v2.0 Adds mixed signal and I/O capability Adds high frequency low noise devices for analog and 2.5V HEMTs for electrical I/O to the PET PDK. Update PDK with new devices and calibra+on. Op+cal On-‐Chip Signal Distribu+on Components Develop and successful demonstra+on of individual components necessary to build WDM op+cal distribu+on and conversion from E-‐O and O-‐E. SRAM Structure Develop and successful demonstra+on of 2T thyristor-‐based bit cell, read and write amps. Goal of layout density greater than equivalent CMOS bit cell at same node. Demonstra+on Digital Cell Library Create basic set of digital cells suitable for trial SoC block post layout performance evalua+on. * Note: Please see Milestone Disclaimer on the next page © 2014 POET Technologies Inc. – Corporate Presentation January 2015 21 Milestone Disclaimer The Milestone schedule contained in this presentation was prepared in good faith; however, the Company does not warrant that it will achieve any results projected in this presentation. This presentation contains "forward-looking information" (within the meaning of applicable Canadian securities laws) and "forward -looking statements" (within the meaning of the U.S. Private Securities Litigation Reform Act of 1995). Such statements include all aspects of the milestones scheduled to be performed after the date of this presentation. Such forward-looking information or statements are based on a number of risks, uncertainties and assumptions which may cause actual results or other expectations to differ materially from those anticipated and which may prove to be incorrect. Assumptions have been made regarding, among other things, plans for and completion of projects by the Company’s third party relationships, availability of capital, and the necessity to incur capital and other expenditures. Actual results could differ materially due to a number of factors, including, without limitation, operational risks in the completion of the Company’s anticipated projects, delays or changes in plans with respect to the development of the Company’s anticipated projects by the Company’s third party relationships, risks affecting the Company’s ability to execute projects, the ability to attract and retain key personnel, and the inability to raise additional capital. Although the Company believes that the expectations reflected in the forward-looking information or statements are reasonable, you should not place undue reliance on forward-looking statements because the Company can provide no assurance that such expectations will prove to be correct. Forward- looking information and statements contained in this presentation are as of the date of this presentation and the Company assumes no obligation to update or revise this forward-looking information and statements except as required by law. © 2014 POET Technologies Inc. – Corporate Presentation January 2015 22 Operational Roadmap Expansion of POET Lab Facility into a 3rd Party Fab § Provides POET with operational backup plan (disaster relief) § Increase the capacity of our R&D process and device IP development § Replication and transfer of current process at a larger scale • Multi-wafer and multi-lot § Automated production manufacturing with concurrent development capability • ISO Certified Facility § 3” and 6” wafer sizes capabilities § Packaging, package and wafer level automated test capabilities § Prototyping capability at 100-nm critical features with a goal to reduce to 40-nm © 2014 POET Technologies Inc. – Corporate Presentation January 2015 23 Summary POET - Ready at the right time § Silicon CMOS evolution is ending § POET will provide a much needed performance and power correction to Moore’s Law § Industry’s doubt that Silicon CMOS nodes of 10 and 7nm will succeed § Industry is ready for a paradigm shift for the fabrication of complementary logic semiconductor devices POET enables new innovations § POET enables mixing on the same chip analog, digital and optical devices that will lead to new innovative products and device consolidation never before possible § POET offers a III-V process with very high performance gains over Silicon CMOS § POET low voltage operation enables up to a 90% application power savings POET enables system cost savings § Possible device consolidation will lower manufacturing costs at the module and system level § POET will enable much lower system OPEX due to application power savings © 2014 POET Technologies Inc. – Corporate Presentation January 2015 24
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