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2015 International Symposium on Physical Design
With a Tribute to Dr. Kurt Antreich
Monterey, California, March 29-April 1, 2015
www.ispd.cc
Sponsored by ACM/SIGDA with Technical Co-Sponsorship from IEEE CAS
Additional support from Altera, ATopTech, Cadence, IBM, Intel, Mentor Graphics, Oracle,
Qualcomm and Synopsys
PROGRAM
The International Symposium on Physical Design
provides a high-quality forum for the exchange of ideas
on the physical layout design of VLSI, biological or other
advanced technology systems. The scope of this
symposium includes all aspects of physical design, from
high-level interactions with logic synthesis, down to backend performance optimization and design for
manufacturing.
Regular presentations are 30 minutes.
SUNDAY, March 29
5:30 – 7:00 pm: Reception
MONDAY, March 30
(Invited) “Automation of Analog IC Layout -- Challenges
and Solutions”, Juergen Scheible and Jens Lienig.
12:30 – 2:00 pm: Lunch
2:00 – 3:30 pm Session 2: Learning Physical Design
“Q-Learning Based Dynamic Voltage Scaling for Designs
with Graceful Degradation”, Yu-Guang Chen, Wan-Yu Wen,
Tao Wang, Yiyu Shi and Shih-Chieh Chang.
“SVM-Based Routability-Driven Chip-Level Design for
Voltage-Aware Pin-Constrained EWOD Chips”, Qin
Wang, Weiran He, Hailong Yao, Tsung-Yi Ho and Yici Cai.
(Invited) “Machine Learning in Simulation-based
Analysis”, Li-C. Wang and Malgorzata Marek-Sadowska.
8:45 – 10:00 am: Welcome and Keynote Address
Host: Azadeh Davoodi (UW-Madison)
Monday Keynote:
“3D VLSI: A Scalable Integration Beyond 2D” Karim
Arabi (Qualcomm).
10:00 – 10:30 am: Morning Break
10:30 am - 12:30 pm Session 1: Advanced Placement
“A Self-Stabilizing Placement Framework”, Philipp
Ochsendorf, Nils Hoppmann, Anna Hermann and Ulrich
Brenner.
“Coarse-grained Structural Placement for a Synthesized
Parallel Multiplier”, Sungmin Bae.
“Common-Centroid FinFET Placement Considering the
Impact of Gate Misalignment”, Po-Hsun Wu, Mark PoHung Lin, Li Xin and Tsung-Yi Ho.
3:30 – 4:00 pm: Afternoon Break
4:00 – 5:30 pm Session 3: DFM
(Invited) “Physical Layout Design of Directed Selfassembly Guiding Alphabet for IC Contact Hole/via
Patterning”, H.-S. Philip Wong, He Yi, Maryann Tung, Kye
Okabe.
“A Cell-Based Row-Structure Layout Decomposer for
Triple Patterning Lithography”, Hsi-An Chien, Szu-Yaun
Han, Ye-Hong Chen and Ting-Chi Wang.
“TPL-aware Displacement-driven Detailed Placement
Refinement With Coloring Constraints”, Tao Lin and
Chris Chu.
6:00 – 8:00 pm: Dinner Banquet
(Invited) “Concept & Research to Revenue: An
Entrepreneurial Story” by Dean Drako (IC Manage).
TUESDAY, March 31
9:00 – 10:00 am: Tuesday Keynote Address
Tuesday Keynote:
“Analog Circuit and Layout Synthesis Revisited”, Rob
Rutenbar (UIUC).
10:00 – 10:30 am: Morning Break
10:30 am – 12:00 pm Session 4: Clocking and Power
“A Study On the Construction of Buffered Useful Skew
Clock Trees”, Rickard Ewetz and Cheng-Kok Koh.
“Analytical Clustering Score with Application to PostPlacement Multi-Bit Flip-Flop Merging”, Chang Xu,
Peixin Li, Guojie Luo, Yiyu Shi and Iris Hui-Ru Jiang.
(Invited) “Physical Design Challenge in the Chip Power
Distribution Network”, Farid Najm (U of Toronto).
12:00 – 1:30 pm: Lunch
1:30 – 3:30pm Session 5: Physical Design and
Beyond
“Accelerated Path-Based Timing Analysis with
MapReduce”, Tsung-Wei Huang and Martin D. F. Wong.
“Blech Effect in Interconnects: Applications and Design
Guidelines”, Ali Abbasinasab and Malgorzata MarekSadowska.
“On Resilient System Performance Binning”, Qiang Han,
Jianghao Guo, Qiang Xu and Wen-Ben Jone.
(Invited) “From 2D to Monolithic 3D: Design
Possibilities, Expectations and Challenges”, Olivier Billoint
(LETI).
(Invited) “Life Beyond and After GORDIAN and
KRAFTWERK: The Breadth of Kurt Antreich’s
Research and His Legacy”, Ulf Schlichtmann (Technische
Universität München).
6:00 – 8:30 pm: Dinner Banquet
WEDNESDAY, April 1
8:30 am – 10:00 pm Session 7: Placement and
Contest
“Timing-Driven Placement Based on Dynamic NetWeighting for Efficient Slack Histogram Compression”,
Chrystian Guth, Vinicius Livramento, Renan Netto, Renan
Fonseca, José Luís Güntzel and Luiz Santos.
“Closing the Gap between Global and Detailed
Placement: Techniques for Improving Routability”, Chun
Kai Wang, Chuan Chia Huang, Shih Ying Liu, Ching Yu Chin,
Sheng Te Hu, Wei Chen Wu and Hung Ming Chen.
(Invited) “ISPD 2015 Benchmarks with Fence Regions
and Routing Blockages for Detailed-Routing-Driven
Placement”, Ismail S. Bustany, David Chinnery, Joseph R.
Shinnerl and Vladimir Yutsis (Mentor Graphics).
10:00 – 10:30 am: Morning Break
10:30 am – 12:00 pm Session 8: FreePDK
(Invited) “FreePDK15: An Open-Source Predictive
Process Design Kit for 15nm FinFET Technology”,
Kirti Bhanushali and Rhett Davis.
(Invited) “Open Cell Library in 15nm FreePDK
Technology”, Mayler Martins, Jody Matos, Renato Ribas,
Andre Reis, Guilherme Schlinker, Lucio Rech and Jens Michelsen.
3:30 – 4:00 pm: Afternoon Break
(Invited) “Design Rule Management and its Applications
in 15nm FreePDK Technology”, Michiel Oostindie, Maarten
Berkens and Coby Zelnik.
4:00-5:30 pm Session 6: Commemoration for Dr.
Kurt Antreich
(Invited) “A Benchmark Suite to Jointly Consider Logic
Synthesis and Physical Design”, Jody Matos, Augusto
Neutzling, Renato Ribas and Andre Reis.
(Invited) “The Early Days of Analytical Placement”,
Martin D.F. Wong (UIUC).
(Invited) “Force-directed Quadratic Placement at the
Munich EDA Institute”, Hans Eisenmann (PDF Solutions
GmbH).
12:00 pm – 12:10 pm: Closing Remarks
12:10 – 1:30 pm: Lunch