High-Performance, Multi-I/O, RPMC SPI NOR FLASH PC BIOS Micron SPI NOR Flash for PC BIOS ® Finding a serial peripheral interface (SPI) NOR Flash solution that’s right for your PC BIOS application is easy when you have access to one of the industry’s broadest SPI NOR product portfolios. Our SPI NOR product line is tailored to meet PC BIOS application requirements, including replay-protected monotonic counter (RPMC)-based security needs. Your design will benefit from dramatic read performance, flexible memory partitioning, small package sizes, and a range of density and packaging options. Meet Security Requirements RPMC significantly enhances preboot security in cost-sensitive embedded, mobile, and personal computing architectures. Our RPMC-enabled device facilitates critical nonvolatile data storage while making systems resistant to rollback and replay attacks. It enables designers to strengthen code/data storage in the boot memory and deliver increased security. SPI NOR Solutions – N25Q • Single, dual, quad SPI I/O •16Mb–1Gb • 1.8V or 3V • 108 MHz sync reads (54 MB/s) • DFN, SOP, PBGA packages Contact Us Visit micron.com for more details on SPI NOR Flash solutions. 4 Reasons Why Micron SPI NOR Flash Is Right for Your PC BIOS Design 1. Broad Portfolio Get a flexible, efficient board design when you choose from a wide range of densities and reduced ball count package options. 2. High Read Throughput Achieve faster boot-up with quad I/O and 54 MB/s read speeds. 3. Flexible Memory Partitioning Manage data with greater efficiency with uniform 4KB and 64KB subsector erase. 4. Enhanced Security Strengthen code and data storage and ensure increased security. Micron SPI NOR Flash for PC BIOS SPI NOR Flash Features by Density Features/Options 16Mb 32Mb 64Mb 128Mb 256Mb 512Mb Interface Double transfer rate Device Power-Up Configuration NVCR and VCR XIP mode Sectorization Uniform 4KB and 64KB subsector erase Security UID preprogrammed + 64B user OTP Permanent block lock Replay-protected monotonic counter Other Serial Flash discovery parameter RPMC Features Micron’s 64Mb RPMC-enabled SPI NOR device supports nonvolatile storage and authentication needs that are critical to the chipset security implementation for future Intel® Ultrabook platforms and is compliant with Intel’s Serial Flash Hardening Product External Architecture Specification. Security Compliance Additional Costs “On-Chip” RPMC Using RTC SPI NOR RPMC With Intel Integrated TPM SPI NOR With External TPM Chip + (weak) Not TPM 2.0-compliant $0 ++ (strong) – Minimal cost +++ (stronger) TPM 2.0-compliant/certified Significant cost adder RPMC Benefits • Counters powered by RTC • Data lost due to RTC power loss • Stores counters in SPI Flash How RPMC Solves Challenges • Removes dependency on RTC • Improved user experience Favorable Outcomes • TPM 2.0-compliant • Platform hardening User Experience • Eliminates 120-minute delay in case of 10 consecutive RTC power loss events Security • TPM storage hierarchy is replay protected Opportunities for OEMs • Replay protection on user data Challenges to Overcome micron.com Products are warranted only to meet Micron’s production data sheet specifications. Products and specifications are subject to change without notice. Dates are estimates only. ©2015 Micron Technology, Inc. All rights reserved. Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. Rev. 02/15