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ECE 3829: Advanced Digital System Design using FPGAs
C term 2015
Exam 2: February 17, 2015 (11.00 to 11.50)
Solutions
This exam is closed book (no books or notes or electronic devices allowed).
A page of Verilog notes will be provided (see last page).
Read each question carefully
Use a standard and consistent coding style.
Try and answer each question - if you consider any question to be ambiguous then
state any assumptions you make.
NAME: ___________________________
ECE Box: ________________________
ECE3829: Advanced Digital System Design using FPGAs
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Question 1 [10 marks]: Write a complete Verilog synthesizable module description of a circuit
with the inputs and outputs as shown in the block diagram below (the ‘bus’ ports are all 32-bits
in size:
OE_N
A_BUS
B_BUS
C_BUS
LOAD
When the output enable ‘OE_N’ signal is low then the ‘B_BUS’ bidirectional port should have
the value of the ‘A_BUS’ input port.
When the ‘OE_N’ signal is high then the ‘B_BUS’ port should go to tri-state.
On a rising edge of the load signal the value on the ‘B_BUS’ should be loaded into 32 flip-flops.
The output of the flip-flops should be connected to the output port ‘C_BUS’.
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Question 2 [60 marks]: In Verilog, design a synthesizable system that consists of:
A four state state-machine controlling the loading and right shift of a 20-bit shift-register.
The state machine waits in S0 until it receives an active high input start signal;
It then goes from S0 to S1;
In S1 it causes the 20-bit shift register to be loaded with a value on a 20-bit data bus;
In S2 it sends a signal to start the shift register;
It then waits in S3 until the shift register has completed shifting out the 20 bits
The state machine then returns to state 0 and waits for the start signal to go high again
Notes:
There is an active high asynchronous reset and a positive edge triggered clk.
Assume the start input signal is high for no more than two clock cycles.
The shift register shifts right and the shift output is connected to the least significant bit.
Design the shift register as a separate module and then instantiate it at the top level.
A simplified block diagram of the system is shown below.
CLK
RESET
Shift_Register
Module
START
SHIFT
DATA
State Machine
How many flip-flops will be required to implement this system (explain)?
20 for shift register, 5 for counter (0-20), 2 (or 4) for state machine. Total = 27 (or 29)
The start of the top-level module description is provided:
module top_shift (
input
input
input
input [19:0]
output
);
clk,
reset,
start,
data,
shift
//
//
//
//
//
positive edge triggered clock
async reset
start operation
data to load into shift register
lsb of shift register
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Example solution shown (for a 10-bit shift register version):
ECE3829: Advanced Digital System Design using FPGAs
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ECE3829: Advanced Digital System Design using FPGAs
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Question 3 [15 marks]: Change the Verilog description of the counter below so that it can be
modified to any size when it is instantiated instead of being a fixed width of 5-bits. You can
show the modifications by clearly adding the necessary additional statements to the provided
description:
Also q == ((1<<SIZE) – 1) is acceptable
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Below is the start of a new module that needs to instantiate two copies of the modified counter
register. Each counter will be connected to the clk, clear, q, and tc ports. Write the two
instantiation statements (use named association) to instantiate the two copies of the different
sized counters:
module two_counter (
input
clk,
input
clear,
output [9:0] q1,
output
tc1,
output [15:0] q2,
output
tc2
);
// unique connections to first counter
// unique connections to second counter
Example solution shown:
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Question 4 [15 marks]: Complete the Verilog model of an SRAM memory device with the
following specifications:
Read operation:
Output the correct data only when OE_N and CE_N are both low, otherwise the data bus should
be set to tristate.
Delay the output by 70ns to represent the memory access time.
Write operation:
Write data on the rising edge of WE_N but only if CE_N is low.
(You do not need to check for setup or hold times.)
module sram_model (
input [5:0]
inout [15:0]
input
input
input
);
addr,
data,
ce_n,
oe_n,
we_n
// address bus
// data bus
// active low control signals
Example solution shown (change addr to 5:0 = 64 memory cells, and data width to 16):
ECE3829: Advanced Digital System Design using FPGAs
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