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AICTE Funded Two Week FDP on “Electronic System Design: From Devices to Applications”(4 May 2015 to 15 May 2015)
Inaugural Speech
Dr. S. S. Mantha
Ex-Chairman, All India Council for Technical Education New Delhi
Dr S S Mantha, an eminent academician and an able administrator, is
the Ex-Chairman of the All India Council for Technical Education
(AICTE). Dr Mantha joined the organisation in March 2009 as its
Vice-Chairman, and since then he has been at the forefront of bringing
in some radical changes for transparency and accountability in its
administration.
He progressed to be the Professor and Head, Department of
Mechanical Engineering – a position he held at VJTI, subsequent to which he was appointed the pro
vice chancellor, SNDT Women‟s University by the Government of Maharashtra. He implemented the
first e–Governance project, automating the workflow for the department of Higher and Technical
Education, Government of Maharashtra, in 1995. Further he provided the IT expertise for IT
initiatives of several departments of Government of Maharashtra
He specializes in Robotics which he taught for more than 15 years out of a reach teaching experience
of more than 25 years, along with courses in control theory and artificial intelligence. He was
instrumental in setting up a state of art Robotics/CAD/CAM laboratory at VJTI, providing
consultancy in the area of industrial automation to the industries in Mumbai and Pune. His research
interest in the area also has seen him provide expertise to DRDO and BARC projects.
Sardar Patel Institute of Technology, Andheri (West), Mumbai
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AICTE Funded Two Week FDP on “Electronic System Design: From Devices to Applications”(4 May 2015 to 15 May 2015)
Nanotechnology & the Internet-of-Things
Dr. V.Ramgopal Rao, FNAE, FNA, FASc, FNASc
P.K.Kelkar Chair Professor for Nanotechnology, Department of Electrical Engineering
IIT Bombay, Powai, Mumbai-400076, India
Email: [email protected]
Conventional device technologies usually employ top-down fabrication methodologies for high volume
manufacturing. However, as we enter the nano-scale regime and the Internet of Things (IoT) era, there
are many challenges faced by the conventional top down approaches owing to the variability
&reliability issues. Some of these issues with respect to the conventional technologies can be better
addressed by employing a host of bottom up approaches through innovative process integration
strategies. Further, there is also a need for an intelligent integration of diverse technologies, materials
and processes on the same die or in a package for realization of future smart systems for theIoT Era.
This talk will present some of these integration methodologies where completely diverse platforms,
materials and approaches are brought together in order to realize a targeted system functionality
useful for the IoT applications.
Dr. V. Ramgopal Rao is a P.K.Kelkar Chair Professor for Nanotechnology in
the Department of Electrical Engineering and the Chief Investigator for the
Centre of Excellence in Nanoelectronics project at IIT Bombay. Dr. Rao has
over 350 publications in the area of Electron Devices &Nanoelectronics in
refereed international journals and conference proceedings and is an inventor
on 30 patents (including 13 issued US patents) and patent applications, with
many of his patents licensed to industries for commercialization. He is also a
co-founder of the company NanoSniff Technologies Pvt. Ltd. at IIT Bombay
which is developing products in the area of Nanotechnology. Prof. Rao has supervised/co-supervised over 100
Masters students &30 Ph.D. students at IIT Bombay in the area of Nanoelectronics since the year 2000.
Prof. Rao‟s work is recognized with many awards and honors in the country and abroad. Some of the notable
recognitions he received include the Shanti Swarup Bhatnagar Prize in Engineering Sciences in 2005 and the
Infosys Prize in 2013. Dr. Rao is also a recipient of the Swarnajayanti Fellowship award from the Department
of Science & Technology, IBM Faculty award, Best Research award from the Intel Asia Academic Forum,
Techno-Mentor award from the Indian Semiconductor Association, DAE-SRC Outstanding Research
Investigator award and the Excellence in Research Award from IIT Bombay. Prof. Rao was an Editor for the
IEEE Transactions on Electron Devices during 2003-2012 for the CMOS Devices and Technology area and
currently serves on the Editorial boards of various other international journals. Dr. Rao is a Fellow of the
Indian National Academy of Engineering, the Indian Academy of Sciences, the Indian National Science
Academy, and the National Academy of Sciences. He is a Distinguished Lecturer, IEEE Electron Devices
Society and interacts closely with many semiconductor industries including Intel, IBM, Infineon, Applied
Materials, Maxim and Texas Instruments.
For more information about Prof. Rao’s current research interests and a list of publications visit:
http://www.ee.iitb.ac.in/~rrao/
Sardar Patel Institute of Technology, Andheri (West), Mumbai
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AICTE Funded Two Week FDP on “Electronic System Design: From Devices to Applications”(4 May 2015 to 15 May 2015)
MEMS and NEMS Laboratory
Dr. Nitin Kale
Chief Technology Officer
Nanosniff Technologies Pvt. Ltd.
Piezo-resistive MEMS and NEMS cantilevers can be functionalized as sensors and used for various
applications. This opens up the scope of using this generic cantilever platform for numerous
applications as sensors and for detection, analysis and characterization studies on surface chemical
interaction. Micro-heaters, designed and fabricated by NanoSniff Technologies find their use in
various applications such as small volume gas heating, sources for generation of wide band IR,
ignition etc.
Dr. Nitin Kale secured his B.E and M. Tech. in Electronics Engineering from the Nagpur
University and was awarded the Doctorate of Philosophy by IIT Bombay, specializing in
Microelectronics. Dr. Nitin has also served as a faculty at the YC College of Engineering,
Nagpur and the Nirma Institute of Technology, Ahmedabad. He possesses rich industry
experience in Micro Fabrication having worked at the Taiwan Semiconductor Manufacturing
Company at Hscichu Taiwan. He also has been the Facility Manager for the IIT Bombay Nanofabrication Facility, responsible for all of its day-to-day operations. He has over 15 publications
in referred journals and conferences. As the Chief Technology Officer of NanoSniff Technologies, he looks after the
overall R&D activities and is responsible for the company's research output in design, simulation and fabrication of
MEMS devices and New Products.
TCAD Modeling Using: VISUAL TCAD & 3D Device Simulator GENIUS
Design of 3D novel Device with TCAD
Mr. Amit Saini
Sr. Engineer
Cadre Design Systems Delhi.
VisualTCAD is the latest graphical user interface for the Genius device simulator. VisualTCAD is
designed to suit novice TCAD users and students, and focuses on ease of use. On the other hand, it
doesn't sacrifice the power of Genius. All the physical models and options are accessible with
VisualTCAD. It combines with the Genius Device Simulator to create a next-generation TCAD
solution. Genius is a parallel 2D/3D TCAD device simulator, featuring a wide range of advanced
physical models and simulation capabilities. With Genius, one is able to routinely simulate circuit
cells like inverter, 6T SRAM, latch and flip-flop, and expect 10 fold reduction in simulation run times.
Mr. Amit Saini is B.Tech in Electronics and Communication from SIET Saharanpur, Uttar
Pradesh Technical University. He worked as a lecturer at Shobhit Institute of Engineering and
Technology. He was project Research Associate at IIT Delhi. He worked as Sr Application
Engineer at Integrated Microsystem, Spectra Innovation Pvt. Ltd. and Techlab Pvt. ltd. Currently
he is Engineer at Cadre Design Systems Delhi. His area of Interest is TCAD and Device
Simulation. He provides industrial consultancy and training on ASIC Design and TCAD Design.
Sardar Patel Institute of Technology, Andheri (West), Mumbai
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AICTE Funded Two Week FDP on “Electronic System Design: From Devices to Applications”(4 May 2015 to 15 May 2015)
CMOS Analog Design
Dr. Maryam Shojaei Baghini
Department of Electrical Engineering
IIT-Bombay, Powai, Mumbai 400 076, India.
Phone:+91-22-2576-7425
Email: [email protected]
Many types of signal processing have indeed moved to the digital domain, analog circuits have proved
fundamentally necessary in many of today’s complex, high performance systems. The design of analog circuits
itself has evolved together with the technology and the performance requirements. As the device dimensions
shrink, the supply voltage of integrated circuits drops, and analog and digital circuits are fabricated on one
chip, many design issues arise that were unimportant only a decade ago. Such trends demand that the
analysis and design of circuits be accomplished by an in-depth understanding.
Dr. Maryam Shojaei Baghini is Professor at Electrical Engineering Department
Indian Institute of Technology Bombay. She did B. S. in Electrical Engineering
from S. B. Univ. of Kerman, Ph.D. and M.S., both in Electrical Engineering from
Sharif Univ. of Technology and Post Doc. Research at Dept. of Electrical
Engineering, IIT-Bombay. Dr. Maryam Shojaei Baghini received the Richard
Feynman Prize in 2014, ICE (Institute of Civil Engineers), UK. She has 43 journal
publications and 91 conference publications. She has 26 patents. She is co-author
of the books „Applications of Evolutionary Algorithms in VLSI‟ and „Hardware
Development of Wearable ECG Devices‟. More than 12 chips are fabricated and
successfully tested by her.
Her research interests are Technology-aware design (device circuit co-design), Integrated circuits and system
design with emerging devices, Analog/Mixed-signal VLSI design and test, Specific technologies and
performance-optimized analog/mixed-signal/RF circuits & systems for healthcare applications, Integrated
power management for SOC applications, High-speed data transmission and interconnects, Circuit and system
modeling/optimization, Circuit and system design with organic thin film components, RF/Microwave
integrated circuit design, Analog aspects of digital circuits, Sensor-Circuit Integration and Analog/Mixedsignal/RF EDA (CAD tools, theory and implementation) .
Sardar Patel Institute of Technology, Andheri (West), Mumbai
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AICTE Funded Two Week FDP on “Electronic System Design: From Devices to Applications”(4 May 2015 to 15 May 2015)
FinFET Device Circuit Co-Design: Issues and Challenges
Dr. Sudeb Dasgupta
Associate Professor, Microelectronics & VLSI Group,
Department of Electronics & Communication Engineering,
Indian Institute of Technology Roorkee, Uttarakhand-247667, India.
Tel. (Office): +91-1332-285666; Fax: +91-1332- 285368.
Email: [email protected], [email protected]
The race to the next process node of FinFETs becomes more prominent after the Intel's & TSMC's
announcement to use tri-gate technology (FinFETs) commercially in below 20nm node. Last year, the revealed
the 16nm FinFET process that by many measures is one of the most advanced semiconductor technologies.
Most of the other semiconductor industries/foundries are expected to adopt FinFETs at 16/14 nm in order to
keep pace imposed by the Intel and TSMC. However, similar to the problems faced by any new technology,
FinFETs with sub-20 nm feature size also faces several design challenges. Most of these challenges arise due
to technological restriction that again degrades its performances. Although, some performance boosters such
as high permittivity spacers, enhances the device characteristics but has limited applicability in highperformance circuit applications. Researchers also explored various physical configurations/architectures to
alleviate device-circuit co-design to improve the overall performance. However, contradictory observations
have been made with respect to device and circuit immunity to random variations that result in an ambiguity
about their true applicability. Therefore, it is necessary to thoroughly investigate these novel device
architectures with their circuit suitability and tolerance to random variations. Therefore, this tutorial explores
the possibilities of dual-spacer (symmetric and asymmetric) architecture for the purpose and its impact of
high performance logic circuit/SRAM applications with its tolerance limits to random variations.
Dr. Sudeb Dasgupta received the Ph.D. degree from IIT-BHU, Varanasi, India, in
2000. He is currently an Associate Professor with Electronics & Communication
Engineering Department, IIT-Roorkee, India. He is a member of IEEE, EDS, ISTE and
associate member of Institute of Nanotechnology, UK. He has been a technical
committee member International Conference on Micro-to-Nano, 2006; he is also been
nominated as Marquis‟s Who‟s Who in Science in Engineering, USA awarded by
Marquis, 2006, 2007 and 2008 and has been acting as an expert member of The Global
Open University, The Netherlands. He was awarded with Erasmus Mundus Fellowship
of European union in the year 2010 to work in the area of RDF at Politecnico Di
Torino, Italy. He is the recipient of prestigious IUSSTF to work in the area of SRAM testing at University of
Wisconsin at Madison, USA in the year 2011-12. He was also awarded with DAAD Fellowship to work on
Analog Design using Reconfigurable Logic at TU, Dresden, Germany in the year 2013. He has executed
several sponsored research projects from MHRD and MICT Government of India. His current research
interests are ultra low-power memory design, novel semiconductor devices modeling, and radiation effects on
ICs.
Sardar Patel Institute of Technology, Andheri (West), Mumbai
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AICTE Funded Two Week FDP on “Electronic System Design: From Devices to Applications”(4 May 2015 to 15 May 2015)
Graphene: Step Towards Future Electronics
Dr. Santosh Vishvakarma
Assistant Professor
Nanoscale Devices, VLSI Circuit and System Design
Discipline of Electrical Engineering, Indian Institute of Technology, Indore
https://sites.google.com/site/svishvakarma/
Now days, Graphene is being used as a channel material to avoid the problem of mobility. Graphene is a 2-D
atomic layer of carbon atom with unique electronic properties such as high fermi velocity, outstanding carrier
mobility and a high saturation velocity, which makes it suitable for future electronic application. Meanwhile
researchers are really optimistic but less enthusiastic for the use of Graphene in digital circuit design
application. The main hurdle on this way is the band gap property of Graphene. While all other semiconductor
posses a sizable band gap (e.g. Si 1.1eV, Ge .7eV, GaAs= 1.4 eV), natural graphene is a zero band gap
material. The most obvious effect of zero band gap structure is that Graphene based FET with with gapless
channel do not switch off. However there are different approaches to open a gap. First option is to form
graphene nano ribbons (GNR). In GNR band gap is inversely proportional to the width of GNR. So as width
decreases band gap increases but it is very difficult to have a width less than 20nm and it is also affected by
the edge roughness effect. Hence it is very difficult to prepare GNR with small width. Till now gap around
300-400 meV in GNR is obtained with a width of 15nm but a minimum gap of 360- 500 meV is needed for
digital application.
Graphene is also being used as a gate material because of suitable work function tunability. Along with this,
Graphene oxide, bilayer or trilayer graphene are being used as a storage layer in the non- volatile flash
memories. Further, the graphene is very much suitable for RF application because of very high RF performance
parameters. In addition, graphene is also being used as interconnect and offer minimum resistance at
contacts, Due to very high electrical conductivity. With these great potential of Graphene as material,
expected application for future are better touch screen, E paper, foldable OLED etc.
Dr. Santosh Vishvakarma obtained Ph.D. degree on the topic " Analytical Modeling of Low
Leakage MGDG MOSFET and its Application to SRAM " from Microelectronics and VLSI
Group, Department of Electronics and Computer Engineering, Indian Institute of Technology,
Roorkee (IITR) in 2010. He worked as a Post Doctoral Fellow at Unik- University Graduate
Center, Kjeller, Norway with Prof. Tor. A. Fjeldly in the Project COMON (Compact Modeling
Network) on Compact Modeling development and parameter extraction. During post doc tenure,
he develop an analytical model for multigate MOSFET specially Square and Circular crosssection GAA MOSFET. He is recipient of Marie-Curie Fellowship award from European Union
for the project "COMON" (Compact Modeling Network) during the Post Doctoral Fellowship from the period Jan 2009 to
July 2010 at UNIK-University Graduate Center, Norway.
At presently, he is with Discipline of Electrical Engineering, School of Engineering, Indian Institute of Technology,
Indore, MP, India as an Assistant Professor and engaged with teaching, research in the area of Modeling of advanced
MOS device and their application in Circuit & System Design. Dr. Vishvakarma is reviewer of various Journals like IEEE
Transaction on Electron Devices, IEEE Transaction on Nanotechnology, IEEE Transaction on VLSI Integration System,
Elsevier Microelectronics Journal, Elsevier, Solid State Electronics etc. He is a Member of IEEE, Professional Member of
VLSI Society of India, Associate Member of Institute of Nanotechnology, Life member of Indian Microelectronics
Society (IMS), India. He has published 21 Journal papers, 37 conference papers and 2 patents.
Sardar Patel Institute of Technology, Andheri (West), Mumbai
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AICTE Funded Two Week FDP on “Electronic System Design: From Devices to Applications”(4 May 2015 to 15 May 2015)
Strain Engineering in CMOS: Opportunities and Challenges
Dr. Naushad Alam
Assistant Professor
Aligarh Muslim University, Aligarh-202002
Email: [email protected]
Technology scaling, which has contributed towards the tremendous growth of silicon industry, faces
several process and performance related challenges. Consequently, strain engineering has been used
commensurately with physical scaling to achieve performance gain in modern CMOS processes. The
process induced mechanical strain in the channel improves carrier mobility through band
deformation, band splitting, carrier redistribution, reduced scattering rate and reduced effective
mass etc. Several strain engineering techniques, such as compressive/tensile Etch Stop Liner (c/tESL), embedded Silicon-Germanium (eSiGe) source/drain, embedded Silicon-Carbon (eSiC)
source/drain, Stress Memorization Technique (SMT) etc are integrated into a state-of-the-art CMOS
process flow. However, performance enhancement through strain engineering depends upon the
volume of stressor material surrounding the channel of a device. Therefore, strain enhanced
performance gain depends upon various layout parameters such as source/drain length, poly-pitch,
number of fingers sharing an active region, ESL boundary etc. Apart from the intentional stress
sources, mentioned above, stress originating from Shallow Trench Isolation (STI) also causes a
similar variability. This results into unaccounted change in the device and circuit performance.
Traditionally stress-induced variability is handled by applying performance margins to critical paths
– ironically depleting the performance gains most often needed. Therefore, it is essential to model the
stress induced effects so that an effective and predictable design is made possible. This tutorial
elaborates over this problem and presents a stress aware circuit design methodology.
Dr. Naushad Alam received B. Tech. degree in Electronics & Communication
Engineering from Jamia Millia Islamia, New Delhi in 2003, and M. Tech. Degree in
Electronic Circuits & Systems Design from Aligarh Muslim University, Aligarh in
2009. He obtained Ph.D. degree in Microelectronics from Indian Institute of
Technology Roorkee, India in 2013. His doctoral work was on nanoscale circuit
design considering the impact of process-induced mechanical stress. He has published
papers in IEEE Transaction on Electron Devices, IEEE Transaction on Circuits And
Systems, Elsevier's Microelectronics Reliability and in reputed conferences such as IEEE ISQED, IEEE
ISCAS, IWPSD, VDAT, IEEE ISED etc. His name was included in the IEEE TED Golden List of Reviewers
in 2013. He has received two Best Paper Awards at ICSCI-2008 and IMPACT-2013 respectively. His research
interests include robust nanoscale circuit design, low power circuit design, PVT tolerant circuit design, NearThreshold/Sub-Threshold circuit design etc. Presently he is an Assistant Professor at Aligarh Muslim
University, Aligarh.
Sardar Patel Institute of Technology, Andheri (West), Mumbai
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AICTE Funded Two Week FDP on “Electronic System Design: From Devices to Applications”(4 May 2015 to 15 May 2015)
Neuromorphic Engineering
Dr. Jonathan Joshi
Founder and CEO,
Eduvance Mumbai
Emial: [email protected]
Neuromorphic engineering is a concept developed by Carver Mea describing the use of VLSI systems
containing electronic analog circuits to mimic neuro-biological architectures present in the nervous system.
Neuromorphic engineering is a new interdisciplinary subject that takes inspiration from biology, physics,
mathematics, computer science and electronic engineering to design artificial neural systems, such as vision
systems, head-eye systems, auditory processors, and autonomous robots, whose physical architecture and
design principles are based on those of biological nervous systems. A key aspect of neuromorphic engineering
is understanding how the morphology of individual neurons, circuits and overall architectures creates
desirable computations, affects how information is represented, influences robustness to damage,
incorporates learning and development, adapts to local change (plasticity), and facilitates evolutionary
change.
Dr. Jonathan Joshi did his M.S. and Ph.D. from University of Southern California with a
specialization in neuromorphic engineering based on VLSI and embedded systems. He
worked with Cypress Semiconductor and Kitek Technologies Pvt. Ltd. He is
Founder/C.E.O Vanmat Technologies Pvt. Ltd. Presently he is CEO, Eduvance. He has
over 7 years of experience in teaching and education strategy. He has received numerous
teaching awards and research paper awards in the United States and holds a US patent as
well. He received Best Paper Award at Latin American Symposium on Circuits and
Systems. He advises many start up companies and is a director on the board of TDSWala a
unit of E-Tax Services Pvt Ltd. His research interests are Neuromorphic Engineering,
mbed Platform and Programmable system on Chip
Programmable System on Chip
The Cypress University Program
PSoC is a true programmable embedded SoC integrating configurable analog and digital peripheral
functions, memory and a microcontroller on a single chip. With an extremely flexible visual
embedded design methodology that includes preconfigured, user-defined peripherals and
hierarchical schematic entry, you can change your mind as often as you want and stay on schedule.
No more restarting projects from scratch. No more catalogs. No more limitations. Cypress’s
breakthrough PSoC 3 and PSoC 5 architectures extend the world’s only programmable embedded
system design platform, shattering your design limitations. Larger, more complex applications are
easily handled by the PSoC 5 architecture, with its 32-bit 67 MHz ARM Cortex-M3 processor.
Sardar Patel Institute of Technology, Andheri (West), Mumbai
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AICTE Funded Two Week FDP on “Electronic System Design: From Devices to Applications”(4 May 2015 to 15 May 2015)
ARM mbed Platform
ARM University Program
mbed is a platform and operating system for internet-connected devices based on 32-bit ARM Cortex-M
microcontrollers. Such devices are also known as Internet of Things devices. mbed OS provides a C++
Application Framework and component architecture that is used to create device applications, eliminating
much of the low-level work normally associated with MCU code development. The mbed Microcontroller
Board is a demo-board based on an NXP microcontroller, which has an ARM Cortex core. Applications may be
only developed for the mbed platform using the mbed online IDE, a free online code editor and compiler.
Code is written and compiled within a web browser, and compiled on the cloud using the ARMCC C/C++
compiler. The mbed IDE provides a private workspace with ability to import and share code with distributed
version control, and code documentation generation.
Variability aware performance evaluation of nanoscale CMOS Devices and Circuits
Dr. Sudhakar Mande
Professor, Electronics & Telecommunication Engineering
Don Bosco Institute of Technology Mumbai
Increased levels of process variations and consequent yield loss in nanoscale CMOS Integrated
Circuits is major roadblock for the continued CMOS scaling. In order address this issue, first I will
discuss link among process design, device design and circuit design. In addition to this, a systematic
approach for the development of process aware compact model will be discussed. Such compact
models will capture the variations in significant process parameters and translate these variations to
circuit performance using Industry standard circuit simulators like SPICE or SPECTRE. Further, I
will discuss about impact of variability on low power design techniques. Finally, Design of
Experiment (DOE) based dual-Vth approach for variability aware design of low power nanoscale
CMOS design will be discussed.
Dr. Sudhakar Mande did his Ph.D. from Indian Institute of Technology Bombay. He is
Professor in Electronics & Telecommunication Engineering at Don Bosco Institute of
Technology Mumbai. He has 22 years of teaching experience. His area of interest is VLSi,
Microelectronics and VLSI Signal Processing. He is member of Board of Studies of Electronics
& Telecommunication Engineering.
Sardar Patel Institute of Technology, Andheri (West), Mumbai
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AICTE Funded Two Week FDP on “Electronic System Design: From Devices to Applications”(4 May 2015 to 15 May 2015)
System on Chip
Dr. Nisha Sarwade
Associate Professor, Electronics Engineering
Veermata Jijabai Technological Institute Mumbai
Complex digital circuits are now commonly combined with analog circuits as part of the continuing drive
toward higher levels of electronic system integration. For example, complex microprocessors are frequently
combined with high performance analog and mixed‐signal circuits to form so‐called "system‐on‐a‐chip"
devices. An example of this is a single chip modem combining a digital signal processor with precision
analog‐to‐digital and digital‐to‐analog functions on a single silicon die. Such devices offer the semiconductor
customer significant savings in manufacturing costs due to the resulting reduction of chip‐to‐chip
interconnections.
Dr. Nisha Sarwade received B.E. degree in Electronics Engineering from Jiwaji University,
Gwalior and M.E. (Solid State Electronics) and PhD (Electronics Engineering) from University
of Roorkee. She was working as a lecturer at the University of Roorkee during 1983-1987.
Currently she is working as an Associate Professor at the VJTI, Mumbai, India. Her research
interests include Nano Electronics with emphasis on CNT, Compund semiconductors, High-k
dielectrics and flash memories and Microwave circuit design. She has 56 national as well as
international publications to her credit.
Introduction to MEMS
Dr. Deepak Bhoir
Professor and Head of Electronics Engineering Department
Fr. Conceicao Rodrigues College of Engineering Mumbai
MEMS has been identified as one of the most promising technologies for the 21st Century and has the
potential to revolutionize both industrial and consumer products by combining silicon-based microelectronics
with micromachining technology. Its techniques and microsystem-based devices have the potential to
dramatically affect of all of our lives and the way we live. This talk introduces participants to the field of
MEMS, with emphasis on its commercial applications and device fabrication methods. It also describes the
range of MEMS sensors and actuators, the phenomena that can be sensed or acted upon with MEMS devices,
and outlines the major challenges facing the industry.
Dr. D. V. Bhoir did his Ph.D. in Biomedical Instrumentation from V.J.T. I. Mumbai. He has 22
years of teaching and 2 years of industrial experience. He is professor at Fr. Conceicao Rodrigues
College of Engineering Mumbai. He is specialized in Industrial Automation, VLSI Design and
Biomedical Instrumentation, Development of Micro-Controller based Systems and Virtual
Instrumentation based on LAB-VIEW and Design of Mixed VLSI Circuit. He has several journal
and conference publications. He has given consultancy to Meco Industries Mumbai. He has also
given corporate training to L& T on Embedded System. He was resource person at several STTP
and faculty development programmes organized by colleges.
Sardar Patel Institute of Technology, Andheri (West), Mumbai
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AICTE Funded Two Week FDP on “Electronic System Design: From Devices to Applications”(4 May 2015 to 15 May 2015)
Verification , AMS using mentor graphics tools
Mr. Sumit Patil,
Sr. Application Engineer
Trident Technologies, Pune
Analog and mixed-signal SoC designs combine analog and digital content more tightly than ever before. They
increasingly depend on integrated analog blocks such as A to D and D to A converters, phase-locked loops,
and adaptive filters. This increased level of integration puts tremendous pressure on designers. Traditional
design tool flows force designers to develop analog and digital subsystems in isolation, delaying the
integration of these components until IC layout and the testing until after fabrication. Mentor Graphics
provides world-class analog/mixed-signal (AMS) verification solutions for transistor-level circuitry from the
latest FinFET-based process nodes to traditional analog processes. Questa ADMS extends the familiar Questa
verification platform with analog and mixed-signal standard languages while maintaining a unified simulation
environment. ADMS is language neutral; you can combine VHDL-AMS, Verilog-AMS, VHDL, Verilog,
SystemVerilog, SPICE and SystemC anywhere and at any level in the design.
Mr. Sumit Patil did his B.E. from Vishwakarma Institute Of Technology Pune. Currently he is
Sr. Application Engineer at Trident Technologies, Pune. He has worked in major industry
standard EDA tools in backend ASIC. He analyzes technical queries from clients regarding EDA
tools in both ASIC and assist in their project. He has organized and given training on various
industry standard EDA tools to various clients including defense organizations. He was
associated in projects in ASIC physical designing and physical verification based designs in
major DRDO labs. He was also associated in procurement in EDA tool in major industry and
defense organization. He is well versed in HDL coding, physical design, analog layout, verification and backend design.
He has an experties on tools like pyxis, virtuso, calibre, modelsim, xilinx, precesion synthesis, Leonardo spectrum, questa,
tanner, hyperlynx 3DEM, hyperlynx GHZ, expedition, PADS, Labview, CCS, multisim etc.
Vivaldo and Zynq 7000
Mr. Mayur Deshmukh
Application Engineer
COREEL Technologies, Pune
The Vivado Design Suite from Xilinx delivers a SoC-strength, IP-centric and system-centric, next generation
development environment that has been built from the ground up to address the productivity bottlenecks in
system-level integration and implementation. The Vivado Design suite is a Generation Ahead in overall
productivity, ease-of-use, and system level integration capabilities. Based on the Xilinx All programmable SoC
architecture, the Zynq-7000 All Programmable SoCs enable extensive system level differentiation, integration,
and flexibility through hardware, software, and I/O programmability.
Mr. Mayur Deshmukh did his M.Tech. from Jaypee Institute of Information
Technology,Noida in 2009. Presently he is Application Engineer at CoreEL
Technologies Pune. He has Direct Interaction with the clients of Xilinx related with the
requirement in designing and specification, Full hands on Experience on Xilinx
synthesis tool, Mentor Graphics Precision tool and Xilinx vertex and spartan FPGA.
Sardar Patel Institute of Technology, Andheri (West), Mumbai
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AICTE Funded Two Week FDP on “Electronic System Design: From Devices to Applications”(4 May 2015 to 15 May 2015)
Development of Current mode Circuits in VLSI
Dr. Uday Pandit Khot
Professor, Electronics & Telecommunication Engineering,
St. Francis Institute of Technology Mumbai
The circuits using current-mode building blocks have received considerable attention in many filtering and
signal processing applications. Compared to their voltage-mode counterparts, the current-mode building
blocks are attractive because of their wider bandwidth, higher slew rate, and lower power consumption. As a
large number of op-amp based circuits with elegant realization procedures are already available, it is
worthwhile to convert them into the circuits based on current-mode building blocks.
Dr. Uday Pandit Khot obtained his B. E. in Industrial Electronics from Amaravati University in
1991 and M. Tech. from IIT Bombay in 1999. He has done his Ph. D. in “Synthesis of analog
circuits employing current-mode building blocks” from IIT Bombay in January 2010. He served
Bharati Vidyapeeth's Institute of Technology, Navi Mumbai from 1992 to 1999 as a Lecturer. Later,
he served Thadomal Shahani Engineering College (TSEC), Mumbai as an Assistant Professor and
then Associate Professor during 1999 to 2012. He was Head of the EXTC Department in TSEC
since January 2010. Currently, he is a Professor in Electronics and Telecommunication Engineering
Department of St. Francis Institute of Technology, Mumbai. He is a Fellow member of IETE, Member of IEEE, Member
of ISTE, and Member of IE (India). He was an “Executive Committee Member” of Institution of Electronic and
Telecommunication Engineers (IETE) Mumbai Centre (2006 - 2010). He has received The Late Professor Bhaskar
Balkrishna Deshpande Award, for the year 2012, for the best design and development work in “Micro-meter
displacement” in Electronics and Telecommunication Engineering from Mumbai University. He has been listed in the
International Who‟s Who of Professionals Historical Society having demonstrated exemplary achievement and
distinguished contributions to the business community, edition 2010-2011.
He has published more than 30 research papers in National and International journals and conferences. He is a “Review
Committee Member” of IEEE Transactions on Education and Electronics Letters (IET).
He is associated with various universities such as Mumbai University, SNDT University, and NMIMS University for
guiding Research Scholars in the area of Electronics and Telecommunication. His areas of research interest are: Synthesis
and Analysis of Analog Circuits in Current-mode, Fault diagnosis in Analog/Digital Circuits, Mixed-mode circuits,
Microwave circuits, and Mobile Communication.
Issues in Electronic System Design
Mr. Devendra V. Ranade
Affiliation: Embedded Consultant
Email: [email protected]
IC’s and Systems are becoming more and more complex and there is a need for good design analysis
and practice. Integration of general purpose processors and dedicated hardware needs hardware &
software design skills. There are several issues involved in designing and deploying the diversified
electronic products.
Mr. D.V. Ranade did his B.E (Electronics and Power) in 1981 VISVESVARAYA Regional College of
Engineering, (VNIT) Nagpur. He has an experience exceeding three decades of working in the field of
research, development electronics and instrumentation. He is specialized in Electronics Development and
Designing Embedded Controls for various instruments. He has an expertise and diverse experience of working
on various 8-bit and 32-bit ARM processors, „C‟ and Assembly language. He has high level of technical
orientation to applications, design and service.
Sardar Patel Institute of Technology, Andheri (West), Mumbai
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AICTE Funded Two Week FDP on “Electronic System Design: From Devices to Applications”(4 May 2015 to 15 May 2015)
He has acquired technical trainings from Sorvall Inc (division of Dupont. Denver,
U.S.A) in Refrigerated high speed and ultra high speed centrifuges; from Troxller Inc
(North Carolina , U.S.A) in Asphalt moisture measuring instrument, soil moisture
measurement; from L.K.B. Wallac OY (Turku, Finland) in Liquid scintillation
detector, Beta and Gamma counter for studying radio immuno assay; from Unipath
(division of Dupont. San Francisco. U.S.A) in Hematology and Blood Chemistry
analyzer; from Leica (Hearbrugg, Switzerland) in Survey and photogramatory
instruments and from Nikon ( Kawasaki, Japan) in Survey equipments.
He worked as Service Manager - All India service specialist at Scientific Instruments Company Ltd.
Bangalore, Chennai & Delhi from 1982-1996. From 1997 to 2006 he worked with ASHCO INDUSTRIES
LTD , Mumbai where he was Deputy General Manager (Operations) - In charge of Manufacturing , Research
& Development setup. From August 2006 -till date he is Operating as a technical consultant for embedded,
electronic and instrument development.
As a consultant, he is instrumental in providing technical support to a broad range of clients. The client base he
serve deals in a diversified range of products catering to the needs of different application areas. Throughout
these years he has been actively involved in the pre development, development, production and post
production stages of diverse product. Some of his clients are
Ashco industries, Mumbai, Tantrasoft Solutions(I) Pvt.Ltd, Mumbai, SCR Electronics, Dombivali, SRV
Technologies, Dombivali, Aces Enterprise, Vasai, Instruments and Systems, Nagpur, MRK healthcare Pvt Ltd,
Mumbai, Biotech (India),Mumbai, Technosoft Engineering, Thane, Avon corporation ltd Mumbai, Adiv
techno services, Thane / Bangalore, Soda Hub, Hydrabad, Softtact Technologies, Mumbai, Freight Wings Pvt.
Ltd, Mumbai, Flow drain technologies, Mumbai, Medisystems, Mumbai and Veego Instruments, Mumbai.
IOT a current day Tech Trend and its need from Embedded curriculum
Mr Premkumar Vadapalli
Texas Instruments University Program
The Internet of Things (IoT) is the network of physical objects or "things" embedded with electronics,
software, sensors and connectivity to enable it to achieve greater value and service by exchanging
data with the manufacturer, operator and/or other connected devices. Each thing is uniquely
identifiable through its embedded computing system but is able to interoperate within the existing
Internet infrastructure. Main enabling factor of this promising paradigm is the integration of several
technologies and communications solutions. Unquestionably, the main strength of the IoT idea is the
high impact it will have on several aspects of everyday-life and behavior of potential users.
Mr. Premkumar Vadapalli is a Senior Technical Manager at Texas Instruments
India Ltd. He has an B Tech in Computer Science and Engineering from IIT
Bombay and a MS in Computer Science from Colorado State University. He has
been working with Texas Instruments for over 20 years. During his career at TI he
has spent close to 9 years with the SW Tools team, 9 years in Wireless
Organization working with Mobile customers and 1.5 years with the automotive
team. Currently he is with the TI India University Program team since 2014.
Sardar Patel Institute of Technology, Andheri (West), Mumbai
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AICTE Funded Two Week FDP on “Electronic System Design: From Devices to Applications”(4 May 2015 to 15 May 2015)
Low power microcontroller and usage in IOT
Mr Rohit Prajapati
Application Engineer
Edgate Technologies Pvt Ltd. Bangalore
Connectivity can add great value to many embedded applications. In industrial systems, for example,
end equipment can communicate with remote sensors, other end equipment, and a centralized
management console to improve reliability and productivity. Extending connectivity beyond the LAN
out to the WAN is often referred to as the Internet of Things (IoT) or the Internet of Everything (IoE).
For many applications, attaching devices to the IoT cloud provides additional benefits to the entire
ecosystem – end customers, service providers and equipment OEMs.
TI’s ultra-low power MSP430 MCUs have been designed to serve in wireless-enabled applications
with a variety of system architectures. These microcontrollers allows our customers to innovate and
create designs across a wide range of IoT applications, whether high performance or low-power. TI’s
Performance MCUs consist of microcontrollers designed for closed-loop control IoT applications
requiring real-time performance, connectivity, and safety functionality. The Low-power MCUs, which
integrate a power management system with interrupt handling and SRAM/FRAM for real-time data
capture make these devices extremely powerful at ultra-low power levels to preserve battery life in
IoT applications. TI Performance and Low-Power MCUs have a scalable platform to support
consumer, industrial, and HealthTech IoT applications today.
The MSP430 LaunchPad features on-board emulation, which means you can program and debug
your projects without the need for additional tools. All pins of the MSP430G2 device are fanned out
for easy access. These pins make it easy to plug in 20-pin Booster Packs that add additional
functionality like wireless, capacitive touch and more. Booster Pack plug-in modules can really help
your LaunchPad-based projects soar. These innovative tools plug in to the header pins on the
LaunchPad and allow you to explore different applications that your favorite TI MCU can enable.
Mr Rohit Prajapati did his B.E. in Electronics and Telecommunication Engineering from
Vinayaka Mission's Research Foundation – University. Currently he is Application
Engineer at Edgate Technologies Pvt Ltd. Bangalore.
Sardar Patel Institute of Technology, Andheri (West), Mumbai
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AICTE Funded Two Week FDP on “Electronic System Design: From Devices to Applications”(4 May 2015 to 15 May 2015)
Embedded System Application
Mr. Shrikant Velankar
Professor & Dean R&D
Vidyalankar Institute of Technology Mumbai
There are several real life applications of embedded systems. For example the growing number of electronic
systems being incorporated into trains and subway systems are finding a home on the back end of the
computing scheme, typically controlling specialized functions that reside out of passengers’ view. So, in
talking about the modern-day railway engineering market, it is not only the vehicles themselves that need to
be considered, but the technology that is hidden away as well, ensuring passenger safety as well as railway
efficiency.
Prof. Shrikant Velankar did his maters from V.J.T.I Mumbai and currently he is
research scholar at Indian Institute of Technology Bombay. He has 15 years of
industrial and 10 years of teaching experience. He has executed several consultancy
assignments successfully. His area of interest is embedded systems.
Embedded System Design and Embedded C Programming
Dr. Y. S. Rao
Vice-Principal
Sardar Patel Institute of Technology, Mumbai
The hands on training on latest microcontrollers offer the knowledge and exposure about the fastest growing
Embedded Systems Applications. The issues in the design of an entire electronic system from PCB design,
fabrication, and programming to final deployment have numerous challenges.
Dr. Y. S. Rao did Ph.D. from Indian Institute of Technology Bombay. His area of Interest
is Embedded System, Digital Power Electronics, VLSI Design and Wireless Sensor
Networks. He has published several papers in journal and conferences. He received
honorable mention award by IEEE Computer Society, Washington D.C.,USA, at the
International Design Competition (CSIDC-2002), for the project “Swift Doc”. He
regularly conducts workshops on Embedded System Design at the S.P.I.T. and other
institutes. He has given his consultancy to Dan Technocraft Ethuopia, Indra Packing Machines Malad, SNDT
Santacruz, Sanjivani Sugar Ind. Kopargaon, Shirdi Sansthan ICU Shirdi, Johnson and Johnson Santacruz,
Actis Technologies Pvt. Ltd. Andheri and Trio Info.Tech. Pvt. Ltd. Andheri. He has also conducted corporate
training for Trio Info.Tech. Pvt. Ltd. Andheri, Siemens Information Systems Ltd., Khargar and KarRox
Technologies Ltd., Andheri (W).
Sardar Patel Institute of Technology, Andheri (West), Mumbai