DESIGN OF 1.5 FREQUENCY DIVIDER
A Poster presented by GAURAV KUMAR
Roll no:- 212-EC-2135, M.Tech II
INTRODUCTION
CIRCUIT DAIGRAM OF LATCH
BL0CK DAIGRAM OF 1.5 DIVIDE
This poster gives an overview of design of 1.5
frequency divider circuit in 90nm technology.
1.5 dividers circuits that can divide the input
frequency by 1.5. which can reduce the width
of the phase error pulse produced by the phase
detector. In addition, the new frequency
divider offers a large range of multiple
modulus division. The key to this operation is
the notion of “double-edge-triggered” (DET)
flipflops. A DET flip flop incorporates two D
latches driven by
and CLK and a
multiplexer (MUX). When CLK is high, the
one latch is in the sense mode and the another
latch in the hold mode, and vice versa. Let us
now drive the circuit with a “half-rate clock,”
i.e., one whose period is twice the input bit
period.
BLOCK DAIGRAM OF DET FF
RESULTS
Conclusion
CIRCUIT DAIGRAM OF DET FF
CIRCUIT DAIGRAM OF 1.5 DIVIDER
The frequency divider has implemented in a
90nm CMOS technology. By this method, we
get very fast divider circuit but power
Consumption is 2.94147mw when input
frequency is 1 Ghz with power supply 1.8 volt.
we observe that power consumption
increases with input frequency.
References
1. B. Razavi, “Monolithic Phase-Locked Loops and
Clock Recovery Circuits : Theory and Design”, IEEE
February 1996.
2. F.-H. Huang and Y.-J. Chan, “V-Band CMOS
differential-type Injection Locked Frequency
Dividers”, 2006 International Symposium on VLSI
Design, Automation and Test, pp. 1 – 2, April 2006
3. J.-R. Yuan and C. Svensson, “Fast CMOS Nonbinary
Divider and Counter”, Electronics Letters, pp. 1222
– 1223, June 24th, 1993
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