DIGITAL COMPUTER DESIGN Sample Midterm 1. The block diagram and the function table of a 2-‐bit binary counter register with parallel load circuit is shown right. (a) Design this register with D type flip-‐flops and draw the circuit. (b) Design a 6-‐bit binary counter register with Load parallel load using the 2-‐bit binary counter register 0 with parallel load as a block. Explain the operation 0 1 of the circuit with at most two sentences. Load Count D0 D1 Count 0 1 X Clk Q0 Q1 Action Hold Stored Value Count Up Stored Value Load Data 2. The function table and a circuit of a 4-‐bit shift register is shown below. Assuming Q0Q1Q2Q3 output is 1100 and the flip flop is loaded with 0, fill the following table. What does this circuit do? Clock Pulse Clock Q0 Q1 Q2 Q3 0 1 3. Construct a 128K x 32 memory by using 64K x 8 RAM chips shown in figure and a decoder. Show all pin connections. 1 4. The State Machine Diagram of a digital system whose input signals are Reset, Start, Sum and Stop is shown below. Start Reset S0 R0ß 0, R1ß 0,R2ß 0 Start Start Stop S1 R0ß R0+1 Stop Stop S2 S5 R2ß R2+1 Start R1ß R1+1 Stop R2ß R1+R0 Sum S3 Sum S4 Stop (a) Introduce the control signals of this system. Design the control unit with “One Hot State” method using D type flip-‐flops. Show flip-‐flop input equations and output equations of the control signals. (b) Design the datapath which takes the control signals as input using 4-‐bit counter register with parallel load, one 4-‐bit full-‐adder and multiplexers. 4 bit adder 5. (10) A system is to have the following set of register transfers, implemented using buses: Ca : R0←R1 Cb : R3←R1, R1←R4, R4←R0 Cc : R2←R3, R0←R2 Cd : R2←R4, R4←R2 Design this system using dedicated multiplexers method. 2