1. No category

National Taiwan University
Graduate Institute of Electronics Engineering
Department of Electrical Engineering
Physical Design for Nanometer ICs, Spring 2013
June 17, 2013
Handout #14
TA: Hung-Chih Ou
Sample Solutions to Homework #3
1. (10)
(a) See Figure 1.
T
S
Figure 1: An example that Soukup maze router cannot find the shortest path.
(b) See Figure 2.
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Figure 2: An example that Hightower line-search router cannot find a path.
2. (10)
Associate each cell u with two labels: d(u) and b(u), where d(u) is the distance of the shortest path
from source s to u, and b(u) is the minimum number of bends along the shortest path from s to u.
Initialize d(u) = ∞, b(u) = ∞, ∀u 6= s, d(s) = 0 and b(s) = 0.
In the wave propagation phase, the computation of label d’s is the same as the original maze routing
algorithm. Let u be a cell on the wave front and v a neighboring cell of u. The predecessor cell of u is
the cell from which the wave front was propagated for obtaining the minimum b(u). The propagation
direction of u is the direction from the predecessor cell of u to u. The computation of b(v) is as follows.
1 if (d(v) ≥ d(u) + 1) {
2 if (b(v) > b(u) and v is along the propagation direction of u) {
3
b(v) ← b(u);
4
Record u as the predecessor cell of v;
5 }
6 if (b(v) > b(u) + 1 and v is not along the propagation direction of u) {
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b(v) ← b(u) + 1;
8
Record u as the predecessor cell of v;
9 }
10 }
The basic idea is to compare the distance label d’s first and then compare the bend number label b’s.
The value b(v) of a neighboring cell v with d(v) < d(u) stays unchanged because the path from s
through u to v is not the shortest path between s and v.
The backtracking phase is the same as that of the original maze routing algorithm. Note that it
is possible that there may exist several shortest paths with different number of bends. The wave
propagation phase always keeps track of the shortest path with the minimum bend number to allow
the backtracking phase to find such a path.
3. (10) See Figure 3.
4. (10)
(a) For each point, we use octal partition to find its neighbors. The result is shown in the following
table.
R1
R2
R3
R4
a
b
c
b
c
d
c
d
e
c
e
Using the table, we can derive the corresponding spanning graph, as shown in Figure 4(a).
(b) Applying the Kruskal’s MST algorithm in Figure 4(a), we can derive a minimum spanning tree
shown in Figure 4(b). The merging binary tree is shown in Figure 5(a).
Then we build the point-edge table according to the MST and spanning graph. A point-edge pair
{pt , (p1 ,p2 )} is evaluated iff the edge (p1 ,p2 ) is on the MST and one of edges (pt ,p1 ) and (pt ,p2 ) is
in the spanning graph, i.e., pt is connected with p1 or p2 in the spanning graph. The delete edge
is chosen from the merging tree by finding the least common ancestor.
point
d
edge
(c,e)
delete edge
(d,e)
gain
6
The final Steiner tree is shown in Figure 5(b), and the resulting tree cost = 42.
5. (10) See Figure 6.
6. (20)
(a) The maximal sets are a, b, c, d, e. The lower bound of the channel width is 5.
(b) See Figure 7.
(c) See Figure 8.
(d) See Figure 9.
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(o)
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Figure 3: A routing path from S to T using the A*-search routing.
7. (15)
(a) See Figure 10(a). The resulting skew is 0.
(b) See Figure 10(b).
The tapping points T1 and T2 are located at (90, 160) and (70, 20), respectively.
We have t1 = (0.1 × 50)(1 + 0.2 × 50/2) = 30s, C1 = 0.2 × 100 + 1 + 1 = 22F, t2 = (0.1 × 50)(2 +
0.2 × 50/2) = 35s, and C2 = 0.2 × 100 + 2 + 2 = 24F.
3
a
a
b
b
d
d
c
c
e
e
(a)
(b)
Figure 4: (a) The spanning graph. (b) The minimum spanning tree.
a
b
(d, e)
(a, b)
(b, d)
b
(e, c)
a e
c
d
d
c
e
(a)
(b)
Figure 5: point-edge connection method. (a) The merging binary tree. (b) The final Steiner tree.
The tapping point T3 can be determined by:
x=
(35 − 30) + 0.1 × 160(24 + 0.2×160
)
2
= 0.516
0.1 × 160(0.2 × 160 + 22 + 24)
0.516 × 160 ∼
= 83. Thus we locate T3 at (77, 90). The resulting delay is 281.49s, and the resulting
skew is 281.49 − 279.09 = 2.4s.
(c)
t = 0.1x(0.1x + 0.2) + 0.1(0.2(80 − x) + 0.2 × 50 × 2 + 1 + 1) + 0.1 × (80 − x)(0.1 × (80 − x) + 0.2 × 50 × 2 + 1 + 1)
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(d)
(c)
Figure 6: (a) Coarsening stage level 1, (b) coarsening stage level 2, (c) coarsening stage level 3, and (d)
uncoarsening stage.
b
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a
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e
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d
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e
(a)
d
(b)
Figure 7: (a) HCG and (b) VCG.
when x ∼
= 56, t = 93.72 is the minimum delay for the upper half.
t = 0.1y(0.1y + 0.2) + 0.1(0.2(80 − y) + 0.2 × 50 × 2 + 2 + 2) + 0.1 × (80 − y)(0.1 × (80 − y) + 0.2 × 50 × 2 + 2 + 2)
when y ∼
= 61, t = 90.42 is the minimum delay for the lower half.
The skew is 93.72 − 90.42 = 3.3s
8. (10)
5
a
c
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d
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e
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e
a
Figure 8: The result using the constrained left-edge algorithm.
a
c
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e
a
Figure 9: The result using the dogleg channel router.
Figure 11(a) shows the merging segments and the resulting clock tree is shown in Figure 11(b).
9. (20)
(a) See Figure 12. Assume that the distance between source a and the buffer is x. Therefore,
delay
=
100(0.1x + 0.1x + 20) + 0.1x(0.1x + 20)
+
100(0.1(6000 − x) + 0.1(6000 − x) + 20) + 0.1(6000 − x)(0.1(6000 − x) + 20)
= 0.02x2 − 120x + 496000
= 0.02(x − 3000)2 + 316000.
Thus, the buffer can be inserted at 3000um from source a, and the resulting delay is 316000f s.
(b) See Figure 13. Assume that the wire width w. Therefore,
delay
=
100(600w + 600w + 20) + 600/w(600w + 20)
=
120000w + 362000 + 12000/w.
From the equation, delay = 494000f s is minimized as w = 1um. Compared the result with that
of 9(a), buffer insertion is more effective for delay minimization.
10. (10)
a = −0.5, b = 0, c = 0.5, and d = 2.
11. (15)
(a) Functions cx and Ax ≤ b need to be polynomials.
Pm
(b) Dual Feasibility: ∂L(λ)
i=1 (λi ∇gi (x)) = 0.
∂xi = 0 ⇒ ∇f (x) +
T T
] and gi (x) = vi x − bi . Therefore,
Now, f (x) = cx and g(x) = Ax − b. Let AT = [v1T , v2T , ..., vm
∇f (x) +
m
X
(λi ∇gi (x))
= c+
i=1
m
X
(λi vi )
i=1
= c + [v1 , v2 , ..., vm ][λ1 , λ2 , ..., λm ]T
= c + AT λ
=
6
0.
P4 (120, 180)
P4 (120, 180)
P1 (40, 160)
T1 (90, 160)
P1 (40, 160)
T1 (90, 160)
T3 (77, 90)
T3 (80, 90)
P2 (20, 20)
P2 (20, 20)
T2 (70, 20)
T2 (70, 20)
P3 (100, 0)
(a)
P3 (100, 0)
(b)
Figure 10: Routing results of geometric matching (a) by using the linear delay model. (b) by using the
Elmore delay model.
Complementary: λi gi (x) = λi (vi x − bi ) = λ(Ax − b) = 0.
Feasibility: gi (x) ≤ 0, λi ≥ 0. That is, Ax − b ≤ 0, λ ≥ 0.
(c) Our current solution (upper bound) is the optimal solution when it converges to a feasible solution
from Lagrangian relaxation (lower bound).
7
S1
Va
msa
S1
Vc
S0
S2
S0
S2
msc
S4
msb
S3
(a)
S4
Vb
S3
(b)
Figure 11: Clock tree construction based on the DME algorithm. (a) The merging segments. (b) The
resulting clock tree.
a
wire
wire
0.1x
0.1(6000-x)
100
20
0.2(x/2)
100
20
0.2[(6000-x)/2]
buffer
Figure 12: Delay minimization for a buffered wire.
600/w
a
100
b
20
600w
Figure 13: Delay minimization for a sized wire.
8
b