VISHAY IRF73 datasheet

IRF730AS, SiHF730AS, IRF730AL, SiHF730AL
Vishay Siliconix
Power MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
• Low Gate Charge Qg Results in Simple Drive
Requirement
400
RDS(on) (Max.) (Ω)
VGS = 10 V
1.0
Qg (Max.) (nC)
22
Qgs (nC)
5.8
Qgd (nC)
9.3
Configuration
RoHS*
• Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
COMPLIANT
• Fully Characterized Capacitance and Avalanche Voltage
and Current
• Effective Coss Specified
Single
• Lead (Pb)-free Available
D
I2PAK (TO-262)
Available
APPLICATIONS
D2PAK (TO-263)
• Switch Mode Power Supply (SMPS)
• Uninterruptible Power Supply
G
G
• High Sspeed Power Switching
D
S
TYPICAL SMPS TOPOLOGIES
S
• Single Transistor Flyback Xfmr. Reset
N-Channel MOSFET
• Single Transistor Forward Xfmr. Reset
(Both US Line Input Only)
ORDERING INFORMATION
Package
Lead (Pb)-free
SnPb
D2PAK (TO-263)
D2PAK (TO-263)
D2PAK (TO-263)
I2PAK (TO-262)
IRF730ASPbF
SiHF730AS-E3
IRF730AS
SiHF730AS
IRF730ASTRLPbFa
IRF730ASTRRPbFa
SiHF730ASTL-E3a
IRF730ASTRLa
SiHF730ASTLa
SiHF730ASTR-E3a
-
IRF730ALPbF
SiHFL014T-E3
-
Note
a. See device orientation.
ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
LIMIT
Drain-Source Voltage
VDS
400
Gate-Source Voltage
VGS
± 30
VGS at 10 V
Continuous Drain Current
TC = 25 °C
ID
TC = 100 °C
Pulsed Drain Currenta, e
UNIT
V
5.5
3.5
A
IDM
22
0.6
W/°C
Single Pulse Avalanche Energyb, e
EAS
290
mJ
Avalanche Currenta
IAR
5.5
A
Repetiitive Avalanche Energya
EAR
7.4
mJ
PD
74
W
V/ns
Linear Derating Factor
Maximum Power Dissipation
TC = 25 °C
dV/dtc, e
dV/dt
4.6
Operating Junction and Storage Temperature Range
TJ, Tstg
- 55 to + 150
Peak Diode Recovery
Soldering Recommendations (Peak Temperature)
for 10 s
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Starting TJ = 25 °C, L = 19 mH, RG = 25 Ω, IAS = 5.5 A (see fig. 12).
c. ISD ≤ 5.5 A, dI/dt ≤ 90 A/µs, VDD ≤ VDS, TJ ≤ 150 °C.
d. 1.6 mm from case.
e. Uses IRF730A/SiHF730A data and test condition
300d
°C
* Pb containing terminations are not RoHS compliant, exemptions may apply
Document Number: 91046
S-Pending-Rev. A, 30-May-08
WORK-IN-PROGRESS
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IRF730AS, SiHF730AS, IRF730AL, SiHF730AL
Vishay Siliconix
THERMAL RESISTANCE RATINGS
SYMBOL
TYP.
MAX.
Maximum Junction-to-Ambient
(PCB Mounted, steady-state)a
PARAMETER
RthJA
-
40
Maximum Junction-to-Case (Drain)
RthJC
-
1.7
UNIT
°C/W
Note
a. When mounted on 1" square PCB (FR-4 or G-10 material).
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
Gate-Source Threshold Voltage
VDS
VGS = 0 V, ID = 250 µA
400
-
-
V
ΔVDS/TJ
Reference to 25 °C, ID = 1 mAd
-
0.5
-
V/°C
VGS(th)
VDS = VGS, ID = 250 µA
2.0
-
4.5
V
Gate-Source Leakage
IGSS
VGS = ± 30 V
-
-
± 100
nA
Zero Gate Voltage Drain Current
IDSS
VDS = 400 V, VGS = 0 V
-
-
25
VDS = 320 V, VGS = 0 V, TJ = 125 °C
-
-
250
Drain-Source On-State Resistance
Forward Transconductance
RDS(on)
gfs
ID = 3.3 Ab
VGS = 10 V
VDS = 50 V, ID = 3.3 Ad
µA
-
-
1.0
Ω
3.1
-
-
S
-
600
-
-
103
-
Dynamic
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Output Capacitance
Effective Output Capacitance
Coss
VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5d
VGS = 0 V
Coss eff.
Total Gate Charge
Qg
Gate-Source Charge
Qgs
VGS = 10 V
-
4.0
-
VDS = 1.0 V, f = 1.0 MHz
-
890
-
VDS = 320 V, f = 1.0 MHz
-
30
-
VDS = 0 V to 320 Vc, d
-
45
-
-
-
22
ID = 3.5 A, VDS = 3200 V,
see fig. 6 and 13b, d
-
-
5.8
pF
nC
Gate-Drain Charge
Qgd
-
-
9.3
Turn-On Delay Time
td(on)
-
10
-
-
22
-
-
20
-
-
16
-
-
-
5.5
-
-
22
-
-
1.6
-
370
550
ns
-
1.6
2.4
µC
Rise Time
Turn-Off Delay Time
Fall Time
tr
td(off)
VDD = 200 V, ID = 3.5 A,
RG = 12 Ω, RD = 57 Ω, see fig. 10b, d
tf
ns
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulsed Diode Forward Currenta
ISM
Body Diode Voltage
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Forward Turn-On Time
ton
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
S
TJ = 25 °C, IS = 5.5 A, VGS = 0 Vb
TJ = 25 °C, IF = 3.5 A, dI/dt = 100 A/µsb, d
V
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %.
c. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80 % VDS.
d. Uses IRF730A/SiHF730A data and test conditions.
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Document Number: 91046
S-Pending-Rev. A, 30-May-08
IRF730AS, SiHF730AS, IRF730AL, SiHF730AL
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
100
100
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
10
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
1
0.1
4.5V
10
1
10
100
0.1
4.0
VDS, Drain-to-Source Voltage (V)
2.5
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
4.5V
0.1
20µs PULSE WIDTH
TJ= 150 °C
1
10
Fig. 2 - Typical Output Characteristics
Document Number: 91046
S-Pending-Rev. A, 30-May-08
100
RDS(on), Drain-to-Source On Resistance
(Normalized)
ID, Drain-to-Source Current (A)
1
VDS, Drain-to-Source Voltage (V)
5.0
6.0
7.0
8.0
9.0
10.0
Fig. 3 - Typical Transfer Characteristics
TOP
0.01
0.1
VDS = 50V
20µs PULSE WIDTH
VGS, Gate-to-Source Voltage (V)
Fig. 1 - Typical Output Characteristics
10
TJ = 25 °C
1
20µs PULSE WIDTH
TJ= 25 °C
0.01
0.1
100
TJ = 150 °C
ID = 5.5 A
2.0
1.5
1.0
0.5
0.0
-60 -40 -20
VGS = 10V
0
20
40
60
80 100 120 140 160
VGS, Gate-to-Source Voltage (V)
Fig. 4 - Normalized On-Resistance vs. Temperature
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IRF730AS, SiHF730AS, IRF730AL, SiHF730AL
Vishay Siliconix
100
100000
Crss = Cgd
10000
C, Capacitance (pF)
ISD, Reverse Drain Current (A)
VGS = 0V, f = 1 MHz
Ciss = Cgs + Cgd, Cds SHORTED
Coss = Cds + Cgd
1000
Ciss
Coss
100
10
Crss
TJ = 150 °C
10
TJ = 25 °C
1
VGS = 0 V
1
1
10
100
0.1
0.4
1000
ID = 5.5 A
16
0.8
1.0
1.2
Fig. 7 - Typical Source-Drain Diode Forward Voltage
100
OPERATION IN THIS AREA LIMITED
BY RDS(on)
VDS = 320V
VDS = 200V
VDS = 80V
10us
ID, Drain Current (A)
VGS, Gate-to-Source Voltage (V)
20
0.6
VSD, Source-to-Drain Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
12
8
10
100us
1ms
1
10ms
4
0
FOR TEST CIRCUIT
SEE FIGURE 13
0
5
10
15
20
25
VSD, Source-Drain Diode Forward Voltage
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
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TC = 25 °C
TJ = 150 °C
Single Pulse
0.1
10
100
1000
VDS, Drain-to-Source Voltage (V)
Fig. 8 - Maximum Safe Operating Area
Document Number: 91046
S-Pending-Rev. A, 30-May-08
IRF730AS, SiHF730AS, IRF730AL, SiHF730AL
Vishay Siliconix
RD
VDS
6.0
VGS
ID, Drain Current (A)
5.0
D.U.T.
RG
4.0
+
- VDD
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
3.0
Fig. 10a - Switching Time Test Circuit
2.0
VDS
90 %
1.0
0.0
25
50
75
100
125
10 %
VGS
150
TC, Case Temperatrure
td(on)
Fig. 9 - Maximum Drain Current vs. Case Temperature
td(off) tf
tr
Fig. 10b - Switching Time Waveforms
Thermal Response (ZthJC)
10
1
D = 0.50
0.20
0.10
PDM
0.05
0.1
t1
0.02
0.01
t2
SINGLE PULSE
(THERMAL RESPONSE)
0.01
0.00001
0.0001
Notes:
1. Duty factor D = t1 / t2
2. Peak TJ = PDM x ZthJC + TC
0.001
0.01
0.1
1
t1, Rectangular Pulse Duration (sec)
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
VDS
15 V
tp
L
VDS
D.U.T
RG
IAS
20 V
tp
Driver
+
A
- VDD
IAS
0.01 Ω
Fig. 12a - Unclamped Inductive Test Circuit
Document Number: 91046
S-Pending-Rev. A, 30-May-08
Fig. 12b - Unclamped Inductive Waveforms
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IRF730AS, SiHF730AS, IRF730AL, SiHF730AL
Vishay Siliconix
610
TOP
600
BOTTOM
ID
2.5A
3.5A
5.5A
500
400
300
200
100
600
VDSav, Avalanche Voltage (V)
EAS, Single Pulse Avalanche Energy (mJ)
700
590
580
570
560
550
540
0
25
50
75
100
125
150
0.0
1.0
Starting TJ, Junction Temperature (°C)
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
2.0
3.0
4.0
5.0
6.0
IAV, Avalanche Current (A)
Fig. 12d - Typical Drain-to-Source Voltage vs.
Avalanche Current
Current regulator
Same type as D.U.T.
50 kΩ
QG
10 V
12 V
0.2 µF
0.3 µF
QGS
QGD
+
D.U.T.
VG
-
VDS
VGS
3 mA
Charge
IG
ID
Current sampling resistors
Fig. 13a - Maximum Avalanche Energy vs. Drain Current
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Fig. 13b - Gate Charge Test Circuit
Document Number: 91046
S-Pending-Rev. A, 30-May-08
IRF730AS, SiHF730AS, IRF730AL, SiHF730AL
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
RG
•
•
•
•
dV/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by duty factor "D"
D.U.T. - device under test
Driver gate drive
P.W.
+
Period
D=
+
-
VDD
P.W.
Period
VGS = 10 V*
D.U.T. ISD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
VDD
Body diode forward drop
Inductor current
Ripple ≤ 5 %
ISD
* VGS = 5 V for logic level devices
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see http://www.vishay.com/ppg?91046.
Document Number: 91046
S-Pending-Rev. A, 30-May-08
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Disclaimer
All product specifications and data are subject to change without notice.
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(collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein
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Document Number: 91000
Revision: 18-Jul-08
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