IRFP31N50L, SiHFP31N50L
Vishay Siliconix
Power MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
• Super Fast Body Diode Eliminates the Need for
External Diodes in ZVS Applications
500
RDS(on) (Ω)
VGS = 10 V
0.15
Available
RoHS*
Qg (Max.) (nC)
210
Qgs (nC)
58
• Lower Gate Charge Results in Simpler Drive
Requirements
100
• Enhanced dV/dt Capabilities Offer Improved Ruggedness
Qgd (nC)
Configuration
Single
COMPLIANT
• Higher Gate Voltage Threshold Offers Improved Noise
Immunity
D
TO-247
• Lead (Pb)-free Available
APPLICATIONS
G
• Zero Voltage Switching SMPS
• Telecom and Server Power Supplies
S
D
G
• Uninterruptible Power Supplies
S
• Motor Control Applications
N-Channel MOSFET
ORDERING INFORMATION
Package
TO-247
IRFP31N50LPbF
SiHFP31N50L-E3
IRFP31N50L
SiHFP31N50L
Lead (Pb)-free
SnPb
ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
LIMIT
Drain-Source Voltage
VDS
500
Gate-Source Voltage
VGS
± 30
Continuous Drain Current
VGS at 10 V
TC = 25 °C
TC = 100 °C
Pulsed Drain Currenta
ID
UNIT
V
31
20
A
IDM
124
3.7
W/°C
Single Pulse Avalanche Energyb
EAS
460
mJ
Repetitive Avalanche Currenta
IAR
31
A
Repetitive Avalanche Energya
EAR
46
mJ
Linear Derating Factor
Maximum Power Dissipation
TC = 25 °C
Peak Diode Recovery dV/dtc
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
Mounting Torque
for 10 s
6-32 or M3 screw
PD
460
W
dV/dt
19
V/ns
TJ, Tstg
- 55 to + 150
300d
°C
10
lbf · in
1.1
N·m
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Starting TJ = 25 °C, L = 1 mH, RG = 25 Ω, IAS = 31 A (see fig. 12).
c. ISD ≤ 31 A, dI/dt ≤ 422 A/µs, VDD ≤ VDS, TJ ≤ 150 °C.
d. 1.6 mm from case.
* Pb containing terminations are not RoHS compliant, exemptions may apply
Document Number: 91220
S-81274-Rev. A, 16-Jun-08
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IRFP31N50L, SiHFP31N50L
Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER
Maximum Junction-to-Ambient
Case-to-Sink, Flat, Greased Surface
Maximum Junction-to-Case (Drain)
SYMBOL
TYP.
MAX.
UNIT
RthJA
RthCS
RthJC
0.24
-
40
0.26
°C/W
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
Gate-Source Threshold Voltage
Gate-Source Leakage
Zero Gate Voltage Drain Current
Drain-Source On-State Resistance
Forward Transconductance
VDS
VGS = 0 V, ID = 250 µA
500
-
-
V
ΔVDS/TJ
Reference to 25 °C, ID = 1 mA
-
0.28
-
V/°C
VGS(th)
VDS = VGS, ID = 250 µA
3.0
-
5.0
V
VGS = ± 30 V
-
-
± 100
nA
VDS = 500 V, VGS = 0 V
-
-
50
µA
VDS = 400 V, VGS = 0 V, TJ = 125 °C
-
-
2.0
mA
IGSS
IDSS
RDS(on)
gfs
VGS = 10 V
ID = 19
Ab
VDS = 50 V, ID = 19 Ab
-
0.15
0.18
Ω
15
-
-
S
-
5000
-
-
553
-
Dynamic
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Output Capacitance
Coss
Effective Output Capacitance
Coss eff.
Effective Output Capacitance
Coss eff. (ER)
Total Gate Charge
Qgs
Gate-Drain Charge
Qgd
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
VGS = 0 V
-
59
VDS = 1.0 V , f = 1.0 MHz
-
6630
-
VDS = 400 V , f = 1.0 MHz
-
155
-
VDS = 0 V to 400 Vc
Qg
Gate-Source Charge
Internal Gate Resistance
VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5
rG
VGS = 10 V
ID = 31 A, VDS = 400 V,
see fig. 7 and 13b
f = 1 MHz, open drain
td(on)
tr
td(off)
VDD = 250 V, ID = 31 A,
RG = 4.3 Ω, see fig. 10b
tf
-
276
-
-
200
-
-
-
210
-
-
58
-
-
100
-
1.1
-
-
28
-
-
115
-
-
54
-
-
53
-
-
-
31
-
-
124
pF
nC
Ω
ns
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
Pulsed Diode Forward Currenta
Body Diode Voltage
IS
ISM
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Reverse Recovery Current
IRRM
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
TJ = 25 °C, IS = 31 A, VGS = 0
S
Vb
-
-
1.5
TJ = 25 °C, IF = 31 A
-
170
250
V
TJ = 125 °C, dI/dt = 100 A/µsb
-
220
330
TJ = 25 °C, IS = 31 A, VGS = 0 Vb
-
570
860
nC
TJ = 125 °C, dI/dt = 100 A/µsb
-
1.2
1.8
TJ = 25 °C
-
7.9
12
µC
A
ns
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Forward Turn-On Time
ton
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %.
c. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80 % VDS.
Coss eff. (ER) is a fixed capacitance that stores the same energy as Coss while VDS is rising from 0 to 80 % VDS.
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Document Number: 91220
S-81274-Rev. A, 16-Jun-08
IRFP31N50L, SiHFP31N50L
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
ID, Drain-to-Source Current (A)
Top
100
Bottom
1000
VGS
15 V
12 V
10 V
8.0 V
7.0 V
6.0 V
5.5 V
5.0 V
ID, Drain-to-Source Current (A)
100
10
1
5.0 V
0.1
0.01
0.1
1
20 μs PULSE WIDTH
TJ = 25 °C
100
10
100
TJ = 150 °C
10
TJ = 25 °C
1
VDS = 50 V
20 μs PULSE WIDTH
0.1
4
VDS, Drain-to-Source Voltage (V)
100
ID, Drain-to-Source Current (A)
Top
10
Bottom
VGS
15 V
12 V
10 V
8.0 V
7.0 V
6.0 V
5.5 V
5.0 V
5.0 V
1
0.1
20 μs PULSE WIDTH
TJ = 25 °C
0.01
0.1
10
1
VDS, Drain-to-Source Voltage (V)
Fig. 2 - Typical Output Characteristics
Document Number: 91220
S-81274-Rev. A, 16-Jun-08
6
9
8
7
VGS, Gate-to-Source Voltage (V)
10
11
Fig. 3 - Typical Transfer Characteristics
100
RDS(on), Drain-to-Source On Resistance (Normalized)
Fig. 1 - Typical Output Characteristics
5
3.0
ID = 31 A
2.5
2.0
1.5
1.0
0.5
0.0
- 60 - 40 - 20 0
VGS = 10 V
20 40
60 80 100 120 140 160
TJ, Junction Temperature
Fig. 4 - Normalized On-Resistance vs. Temperature
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IRFP31N50L, SiHFP31N50L
Vishay Siliconix
20
10000000
C, Capacitance (pF)
1000000
ID = 31 A
f = 1 MHz
SHORTED
VGS, Gate-to-Source Voltage (V)
VGS = 0 V,
Ciss = Cgs + Cgd, Cds
Crss = Cgd
Coss = Cds + Cgd
10000
Ciss
1000
Coss
100
VDS = 400 V
VDS = 250 V
VDS = 100 V
12
8
4
Crss
10
0
1
1000
100
10
0
VDS, Drain-to-Source Voltage (V)
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
120
40
80
QG, Total Gate Charge (nC)
160
Fig. 7 - Typical Gate Charge vs. Gate-to-Source Voltage
30
1000
ISD, Reverse Drain Current (A)
25
Energy (μs)
20
15
10
100
TJ = 150 °C
10
TJ = 25 °C
1
5
0
0
100
200
300
400
500
600
VDS, Drain-to-Source Voltage (V)
Fig. 6 - Output Capacitance Stored Energy vs. VDS
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0.1
0.2
VGS = 0 V
1.4
1.0
0.6
VSD, Source-to-Drain Voltage (V)
1.8
Fig. 8 - Typical Source Drain Diode Forward Voltage
Document Number: 91220
S-81274-Rev. A, 16-Jun-08
IRFP31N50L, SiHFP31N50L
Vishay Siliconix
RD
VDS
35
VGS
ID, Drain Current (A)
D.U.T.
RG
30
25
+
- VDD
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
20
Fig. 10a - Switching Time Test Circuit
15
VDS
10
90 %
5
0
25
50
75
125
100
10 %
VGS
150
TC, Case Temperature (°C)
td(on)
Fig. 9 - Maximum Drain Current vs. Case Temperature
td(off) tf
tr
Fig. 10b - Switching Time Waveforms
Thermal Response (ZthJC)
1
D = 0.50
0.1
0.20
0.10
0.05
PDM
0.02
0.01
0.01
SINGLE PULSE
(THERMAL RESPONSE)
t1
t2
Notes:
1. Duty factor D = t1/ t2
2. Peak TJ = PDM x ZthJC + TC
0.001
0.00001
0.001
0.0001
0.01
0.1
1
t 1, Rectangular Pulse Duration (sec)
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
VDS
15 V
tp
L
VDS
D.U.T
RG
IAS
20 V
tp
Driver
+
A
- VDD
IAS
0.01 Ω
Fig. 12a - Unclamped Inductive Test Circuit
Document Number: 91220
S-81274-Rev. A, 16-Jun-08
A
Fig. 12b - Unclamped Inductive Waveforms
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IRFP31N50L, SiHFP31N50L
Vishay Siliconix
ID, Drain Current (A)
OPERATION IN THIS AREA LIMITED
BY RDS(on)
100
10us
100us
10
1
1ms
TC = 25 °C
TJ = 150 °C
Single Pulse
10ms
100
10
1000
EAS, Single Pulse Avalanche Energy (mJ)
1000
1000
ID
14A
20A
BOTTOM 30A
TOP
800
600
400
200
0
25
50
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
75
100
125
150
Starting TJ, Junction Temperature(°C)
VDS, Drain-to-Source Voltage (V)
Fig. 12d - Gate Charge Test Circuit
Current regulator
Same type as D.U.T.
QG
VGS
50 kΩ
12 V
0.2 µF
0.3 µF
QGS
QGD
+
D.U.T.
-
VDS
VG
VGS
3 mA
Charge
IG
ID
Current sampling resistors
Fig. 13a - Maximum Safe Operating Area
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Fig. 13b - Basic Gate Charge Waveform
Document Number: 91220
S-81274-Rev. A, 16-Jun-08
IRFP31N50L, SiHFP31N50L
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
•
•
•
•
RG
dV/dt controlled by R G
Driver same type as D.U.T.
ISD controlled by duty factor "D"
D.U.T. - device under test
Driver gate drive
P.W.
+
Period
D=
+
-
VDD
P.W.
Period
VGS = 10 V*
D.U.T. ISD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
VDD
Body diode forward drop
Inductor current
Ripple ≤ 5 %
ISD
* VGS = 5 V for logic level devices
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see http://www.vishay.com/ppg?91220.
Document Number: 91220
S-81274-Rev. A, 16-Jun-08
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Vishay
Disclaimer
All product specifications and data are subject to change without notice.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf
(collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein
or in any other disclosure relating to any product.
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information provided herein to the maximum extent permitted by law. The product specifications do not expand or
otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed
therein, which apply to these products.
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Document Number: 91000
Revision: 18-Jul-08
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