1. No category

IRF740A, SiHF740A
Vishay Siliconix
Power MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
• Low Gate Charge Qg Results in Simple Drive
Available
Requirement
• Improved Gate, Avalanche and Dynamic dV/dt RoHS*
COMPLIANT
Ruggedness
• Fully Characterized Capacitance and Avalanche Voltage
and Current
• Effective Coss Specified
• Lead (Pb)-free Available
400
RDS(on) (Ω)
VGS = 10 V
0.55
Qg (Max.) (nC)
36
Qgs (nC)
9.9
Qgd (nC)
16
Configuration
Single
D
TO-220
APPLICATIONS
• Switch Mode Power Supply (SMPS)
• Uninterruptable Power Supply
• High Speed Power Switching
G
S
G
TYPICAL SMPS TOPOLOGIES
D
S
• Single Transistor Flyback Xfmr. Reset
• Single Transistor Forward Xfmr. Reset (Both for US Line
Input Only)
N-Channel MOSFET
ORDERING INFORMATION
Package
TO-220
IRF740APbF
SiHF740A-E3
IRF740A
SiHF740A
Lead (Pb)-free
SnPb
ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted
PARAMETER
Gate-Source Voltage
Continuous Drain Current
VGS at 10 V
TC = 25 °C
TC = 100 °C
Pulsed Drain Currenta
SYMBOL
LIMIT
UNIT
VGS
± 30
V
ID
10
6.3
A
IDM
40
1.0
W/°C
Single Pulse Avalanche Energyb
EAS
630
mJ
Repetitive Avalanche Currenta
IAR
10
A
Repetitive Avalanche Energya
EAR
12.5
mJ
Linear Derating Factor
Maximum Power Dissipation
TC = 25 °C
Peak Diode Recovery dV/dtc
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
Mounting Torque
for 10 s
6-32 or M3 screw
PD
125
W
dV/dt
5.9
V/ns
TJ, Tstg
- 55 to + 150
300d
°C
10
lbf · in
1.1
N·m
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. VDD = 50 V, starting TJ = 25 °C, L = 12.6 mH, RG = 25 Ω IAS = 10 A (see fig. 12).
c. ISD ≤ 10 A, dV/dt ≤ 330 A/µs, VDD ≤ VDS, TJ ≤ 150 °C.
d. 1.6 mm from case.
* Pb containing terminations are not RoHS compliant, exemptions may apply
Document Number: 91051
S-81291-Rev. A, 16-Jun-08
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IRF740A, SiHF740A
Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
Maximum Junction-to-Ambient
RthJA
-
62
Case-to-Sink, Flat, Greased Surface
RthCS
0.50
-
Maximum Junction-to-Case (Drain)
RthJC
-
1.0
UNIT
°C/W
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
VDS
VGS = 0 V, ID = 250 µA
400
-
-
V
ΔVDS/TJ
Reference to 25 °C, ID = 1 mA
-
0.48
-
V/°C
VGS(th)
VDS = VGS, ID = 250 µA
2.0
-
4.0
V
Gate-Source Leakage
IGSS
VGS = ± 30 V
-
-
± 100
nA
Zero Gate Voltage Drain Current
IDSS
VDS = 400 V, VGS = 0 V
-
-
25
VDS = 320 V, VGS = 0 V, TJ = 125 °C
-
-
250
Gate-Source Threshold Voltage
Drain-Source On-State Resistance
Forward Transconductance
RDS(on)
gfs
ID = 6.0 Ab
VGS = 10 V
VDS = 50 V, ID = 6.0 Ab
µA
-
-
0.55
Ω
4.9
-
-
S
-
1030
-
-
170
-
Dynamic
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Output Capacitance
Coss
Effective Output Capacitance
Coss
Total Gate Charge
Qg
Gate-Source Charge
Qgs
VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5
-
7.7
-
VGS = 0 V, VDS = 1.0 V, f = 1.0 MHz
-
1490
-
VGS = 0 V, VDS = 320 V, f = 1.0 MHz
-
52
-
VGS = 0 V, VDS = 0 V to 320 V
-
61
-
-
-
36
-
-
9.9
VGS = 10 V
ID = 10 A, VDS = 320 V,
see fig. 6 and 13b
Gate-Drain Charge
Qgd
-
-
16
Turn-On Delay Time
td(on)
-
10
-
Rise Time
Turn-Off Delay Time
Fall Time
tr
td(off)
VDD = 200 V, ID = 10 A,
RG = 10 Ω, RD = 19.5 Ω, see fig. 10b
tf
pF
nC
-
35
-
-
24
-
-
22
-
-
-
10
-
-
40
-
-
2.0
-
240
360
ns
-
1.9
2.9
µC
ns
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulsed Diode Forward Currenta
ISM
Body Diode Voltage
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Forward Turn-On Time
ton
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
S
TJ = 25 °C, IS = 10 A, VGS = 0 Vb
TJ = 25 °C, IF = 10 A, dI/dt = 100 A/µsb
V
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %.
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Document Number: 91051
S-81291-Rev. A, 16-Jun-08
IRF740A, SiHF740A
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
100
100
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
I D , Drain-to-Source Current (A)
10
1
0.1
4.5V
20μs PULSE WIDTH
TJ = 25 °C
0.01
0.1
1
10
100
TJ = 150 ° C
1
TJ = 25 ° C
0.1
4.0
V DS = 50V
20μs PULSE WIDTH
5.0
6.0
7.0
8.0
9.0
VDS , Drain-to-Source Voltage (V)
VGS , Gate-to-Source Voltage (V)
Fig. 1 - Typical Output Characteristics, TC = 25 °C
Fig. 3 - Typical Transfer Characteristics
100
3.0
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
TOP
I D , Drain-to-Source Current (A)
10
10
1
4.5V
20µs PULSE WIDTH
TJ = 150 ° C
0.1
0.1
1
10
100
VDS , Drain-to-Source Voltage (V)
Fig. 2 - Typical Output Characteristics, TC = 150 °C
Document Number: 91051
S-81291-Rev. A, 16-Jun-08
RDS(on) , Drain-to-Source On Resistance
(Normalized)
I D , Drain-to-Source Current (A)
TOP
10.0
ID = 10A
2.5
2.0
1.5
1.0
0.5
0.0
-60 -40 -20
VGS = 10V
0
20
40
60
80 100 120 140 160
TJ , Junction Temperature ( °C)
Fig. 4 - Normalized On-Resistance vs. Temperature
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IRF740A, SiHF740A
Vishay Siliconix
100
100000
C, Capacitance(pF)
10000
ISD , Reverse Drain Current (A)
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd , Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
Ciss
1000
Coss
100
10
Crss
10
TJ = 150 ° C
TJ = 25 ° C
1
1
1
10
100
1000
0.1
0.2
VDS, Drain-to-Source Voltage (V)
0.6
0.8
1.0
1.2
1.4
Fig. 7 - Typical Source-Drain Diode Forward Voltage
100
ID = 10A
OPERATION IN THIS AREA LIMITED
BY RDS(on)
VDS = 320V
VDS = 200V
VDS = 80V
16
10us
ID , Drain Current (A)
VGS , Gate-to-Source Voltage (V)
0.4
VSD ,Source-to-Drain Voltage (V)
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
20
V GS = 0 V
12
8
100us
10
1ms
4
FOR TEST CIRCUIT
SEE FIGURE 13
0
0
10
20
30
40
1
TC = 25 ° C
TJ = 150 ° C
Single Pulse
10
10ms
100
1000
QG , Total Gate Charge (nC)
VDS , Drain-to-Source Voltage (V)
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
Fig. 8 - Maximum Safe Operating Area
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Document Number: 91051
S-81291-Rev. A, 16-Jun-08
IRF740A, SiHF740A
Vishay Siliconix
RD
VDS
10.0
VGS
D.U.T.
RG
+
- VDD
ID , Drain Current (A)
8.0
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
6.0
Fig. 10a - Switching Time Test Circuit
4.0
VDS
90 %
2.0
0.0
25
50
75
100
125
150
10 %
VGS
TC , Case Temperature ( ° C)
td(on)
Fig. 9 - Maximum Drain Current vs. Case Temperature
td(off) tf
tr
Fig. 10b - Switching Time Waveforms
Thermal Response (Z thJC )
10
1
D = 0.50
0.20
0.10
0.1
0.05
PDM
0.02
0.01
SINGLE PULSE
(THERMAL RESPONSE)
0.01
t1
t2
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJC + TC
0.001
0.00001
0.0001
0.001
0.01
0.1
1
10
t1 , Rectangular Pulse Duration (sec)
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
VDS
15 V
tp
L
VDS
D.U.T
RG
IAS
20 V
tp
Driver
+
A
- VDD
IAS
0.01 Ω
Fig. 12a - Unclamped Inductive Test Circuit
Document Number: 91051
S-81291-Rev. A, 16-Jun-08
Fig. 12b - Unclamped Inductive Waveforms
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IRF740A, SiHF740A
Vishay Siliconix
TOP
1200
BOTTOM
ID
4.5A
6.3A
10A
1000
800
600
400
580
V DSav , Avalanche Voltage ( V )
EAS , Single Pulse Avalanche Energy (mJ)
1400
560
540
520
500
200
480
1.0
0
25
50
75
100
125
2.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
IAV , Avalanche Current ( A)
150
Starting TJ , Junction Temperature ( °C)
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
3.0
Fig. 12d - Typical Drain-to-Source Voltage Vs.
Avalanche Current
Current regulator
Same type as D.U.T.
50 kΩ
QG
VGS
12 V
0.2 µF
0.3 µF
QGS
+
QGD
D.U.T.
VG
-
VDS
VGS
3 mA
Charge
IG
ID
Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform
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Fig. 13b - Gate Charge Test Circuit
Document Number: 91051
S-81291-Rev. A, 16-Jun-08
IRF740A, SiHF740A
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
RG
•
•
•
•
dV/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by duty factor "D"
D.U.T. - device under test
Driver gate drive
P.W.
+
Period
D=
+
-
VDD
P.W.
Period
VGS = 10 V*
D.U.T. ISD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
VDD
Body diode forward drop
Inductor current
Ripple ≤ 5 %
ISD
* VGS = 5 V for logic level devices
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see http://www.vishay.com/ppg?91051.
Document Number: 91051
S-81291-Rev. A, 16-Jun-08
www.vishay.com
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Legal Disclaimer Notice
Vishay
Disclaimer
All product specifications and data are subject to change without notice.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf
(collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein
or in any other disclosure relating to any product.
Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any
information provided herein to the maximum extent permitted by law. The product specifications do not expand or
otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed
therein, which apply to these products.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this
document or by any conduct of Vishay.
The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless
otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such
applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting
from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding
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Product names and markings noted herein may be trademarks of their respective owners.
Document Number: 91000
Revision: 18-Jul-08
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