IRFPS43N50K, SiHFPS43N50K
Vishay Siliconix
Power MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
• Low Gate Charge Qg Results in Simple Drive
Requirement
500
RDS(on) (Ω)
VGS = 10 V
0.078
Qg (Max.) (nC)
350
Qgs (nC)
85
Qgd (nC)
• Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
RoHS*
COMPLIANT
• Fully Characterized Capacitance and Avalanche Voltage
and Current
180
Configuration
Available
Single
• Low RDS(on)
D
• Lead (Pb)-free Available
SUPER-247TM
APPLICATIONS
G
• Switch Mode Power Supply (SMPS)
S
D
G
• Uninterruptible Power Supply
• High Speed Power Switching
S
N-Channel MOSFET
• Hard Switched and High Frequency Circuits
ORDERING INFORMATION
SUPER-247TM
IRFPS43N50KPbF
SiHFPS43N50K-E3
IRFPS43N50K
SiHFPS43N50K
Package
Lead (Pb)-free
SnPb
ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
LIMIT
Drain-Source Voltage
VDS
500
Gate-Source Voltage
VGS
± 30
Continuous Drain Current
VGS at 10 V
TC = 25 °C
TC = 100 °C
Pulsed Drain Currenta
ID
UNIT
V
47
29
A
IDM
190
4.3
W/°C
Single Pulse Avalanche Energyb
EAS
910
mJ
Repetitive Avalanche Currenta
IAR
47
A
EAR
54
mJ
PD
540
W
dV/dt
9.0
V/ns
TJ, Tstg
- 55 to + 150
Linear Derating Factor
Repetitive Avalanche
Energya
Maximum Power Dissipation
TC = 25 °C
Peak Diode Recovery dV/dtc
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
for 10 s
300d
°C
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Starting TJ = 25 °C, L = 0.82 mH, RG = 25 Ω, IAS = 47 A (see fig. 12c).
c. ISD ≤ 47 A, dI/dt ≤ 230 A/µs, VDD ≤ VDS, TJ ≤ 150 °C.
d. 1.6 mm from case.
* Pb containing terminations are not RoHS compliant, exemptions may apply
Document Number: 91262
S-81367-Rev. B, 21-Jul-08
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IRFPS43N50K, SiHFPS43N50K
Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
Maximum Junction-to-Ambient
RthJA
-
40
Case-to-Sink, Flat, Greased Surface
RthCS
0.24
-
Maximum Junction-to-Case (Drain)
RthJC
-
0.23
UNIT
°C/W
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
Gate-Source Threshold Voltage
VDS
VGS = 0 V, ID = 250 µA
500
-
-
V
ΔVDS/TJ
Reference to 25 °C, ID = 1 mA
-
0.60
-
V/°C
VGS(th)
VDS = VGS, ID = 250 µA
3.0
-
5.0
V
Gate-Source Leakage
IGSS
VGS = ± 30 V
-
-
± 100
nA
Zero Gate Voltage Drain Current
IDSS
VDS = 500 V, VGS = 0 V
-
-
50
VDS = 400 V, VGS = 0 V, TJ = 125 °C
-
-
250
Drain-Source On-State Resistance
Forward Transconductance
RDS(on)
gfs
ID = 28 Ab
VGS = 10 V
VDS = 50 V, ID = 28 A
µA
-
0.078
0.090
Ω
23
-
-
S
-
8310
-
-
960
-
Dynamic
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Output Capacitance
Effective Output Capacitance
Coss
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
Turn-On Delay Time
td(on)
Rise Time
Fall Time
VGS = 0 V
Coss eff.
Total Gate Charge
Turn-Off Delay Time
VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5
tr
td(off)
-
120
-
VDS = 1.0 V, f = 1.0 MHz
-
10170
-
VDS = 400 V, f = 1.0 MHz
-
240
-
VDS = 0 V to 400 Vc
-
440
-
-
-
350
ID = 47 A, VDS = 400 V,
see fig. 6 and 13b
-
-
85
VGS = 10 V
VDD = 250 V, ID = 47 A,
RG = 1.0 Ω, see fig. 10b
tf
pF
nC
-
-
180
-
25
-
-
140
-
-
55
-
-
74
-
-
-
47
-
-
190
-
-
1.5
-
620
940
ns
-
14
21
µC
-
38
-
A
ns
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulsed Diode Forward Currenta
ISM
Body Diode Voltage
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Body Diode Recovery Current
Forward Turn-On Time
IRRM
ton
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
S
TJ = 25 °C, IS = 47 A, VGS = 0 Vb
TJ = 25 °C, IF = 47 A, dI/dt = 100 A/µsb
V
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width ≤ 400 µs; duty cycle ≤ 2 %.
c. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80 % VDS.
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Document Number: 91262
S-81367-Rev. B, 21-Jul-08
IRFPS43N50K, SiHFPS43N50K
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
1000
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
TOP
100
I D , Drain-to-Source Current (A)
I D , Drain-to-Source Current (A)
1000
100
10
1
4.5V
0.1
20µs PULSE WIDTH
TJ = 25 °C
0.01
0.1
1
10
10
TJ = 25 ° C
1
0.1
100
VDS , Drain-to-Source Voltage (V)
RDS(on) , Drain-to-Source On Resistance
(Normalized)
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM4.5V
I D , Drain-to-Source Current (A)
10
4.5V
1
20µs PULSE WIDTH
TJ = 150 °C
0.1
0.1
1
10
VDS , Drain-to-Source Voltage (V)
Fig. 2 - Typical Output Characteristics
Document Number: 91262
S-81367-Rev. B, 21-Jul-08
4
5
6
7
8
9
10
11
12
Fig. 3 - Typical Transfer Characteristics
TOP
100
V DS= 50V
20µs PULSE WIDTH
VGS , Gate-to-Source Voltage (V)
Fig. 1 - Typical Output Characteristics
1000
TJ = 150° C
100
3.5
ID = 48A
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-60 -40 -20
VGS = 10V
0
20 40 60
80 100 120 140 160
TJ , Junction Temperature ( ° C)
Fig. 4 - Normalized On-Resistance vs. Temperature
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IRFPS43N50K, SiHFPS43N50K
Vishay Siliconix
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
C, Capacitance(pF)
100000
100
Coss = Cds + Cgd
10000
Ciss
1000
Coss
100
1000
ISD , Reverse Drain Current (A)
1000000
Crss
10
1
10
100
TJ = 150 ° C
10
TJ = 25 ° C
1
0.1
0.2
1000
1.7
2.2
Fig. 7 - Typical Source-Drain Diode Forward Voltage
1000
20
ID = 48A
OPERATION IN THIS AREA LIMITED
BY RDS(on)
V DS= 400V
V DS= 250V
V DS= 100V
ID , Drain Current (A)
VGS , Gate-to-Source Voltage (V)
1.2
VSD ,Source-to-Drain Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
V GS = 0 V
0.7
15
100
10
10us
100us
10
1ms
5
0
0
50
100
150
200
250
300
350
QG , Total Gate Charge (nC)
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
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1
TC = 25 °C
TJ = 150 °C
Single Pulse
10
10ms
100
1000
VDS , Drain-to-Source Voltage (V)
Fig. 8 - Maximum Safe Operating Area
Document Number: 91262
S-81367-Rev. B, 21-Jul-08
IRFPS43N50K, SiHFPS43N50K
Vishay Siliconix
RD
VDS
50
VGS
D.U.T.
RG
+
- VDD
ID , Drain Current (A)
40
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
30
Fig. 10a - Switching Time Test Circuit
20
VDS
90 %
10
0
25
50
75
100
125
10 %
VGS
150
TC , Case Temperature ( °C)
td(on)
Fig. 9 - Maximum Drain Current vs. Case Temperature
td(off) tf
tr
Fig. 10b - Switching Time Waveforms
Thermal Response(Z thJC )
1
0.1
D = 0.50
0.20
0.10
0.05
0.01
PDM
0.02
0.01
t1
SINGLE PULSE
(THERMAL RESPONSE)
t2
Notes:
1. Duty factor D = t 1 / t 2
2. Peak TJ = P DM x Z thJC + TC
0.001
0.00001
0.0001
0.001
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
VDS
15 V
tp
L
VDS
D.U.T
RG
IAS
20 V
tp
Driver
+
A
- VDD
IAS
0.01 Ω
Fig. 12a - Unclamped Inductive Test Circuit
Document Number: 91262
S-81367-Rev. B, 21-Jul-08
Fig. 12b - Unclamped Inductive Waveforms
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IRFPS43N50K, SiHFPS43N50K
Vishay Siliconix
EAS , Single Pulse Avalanche Energy (mJ)
2000
ID
22A
30A
47A
TOP
BOTTOM
1500
1000
500
0
25
50
75
100
125
150
Starting TJ , Junction Temperature ( °C)
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Current regulator
Same type as D.U.T.
50 kΩ
QG
10 V
12 V
0.2 µF
0.3 µF
QGS
QGD
+
D.U.T.
VG
-
VDS
VGS
3 mA
Charge
IG
ID
Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform
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Fig. 13b - Gate Charge Test Circuit
Document Number: 91262
S-81367-Rev. B, 21-Jul-08
IRFPS43N50K, SiHFPS43N50K
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
•
•
•
•
RG
dV/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by duty factor "D"
D.U.T. - device under test
Driver gate drive
P.W.
+
Period
D=
+
-
VDD
P.W.
Period
VGS = 10 V*
D.U.T. ISD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
VDD
Body diode forward drop
Inductor current
Ripple ≤ 5 %
ISD
* VGS = 5 V for logic level devices
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see http://www.vishay.com/ppg?91262.
Document Number: 91262
S-81367-Rev. B, 21-Jul-08
www.vishay.com
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Vishay
Disclaimer
All product specifications and data are subject to change without notice.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf
(collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein
or in any other disclosure relating to any product.
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information provided herein to the maximum extent permitted by law. The product specifications do not expand or
otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed
therein, which apply to these products.
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Document Number: 91000
Revision: 18-Jul-08
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