VISHAY IRF96 datasheet

IRF9610, SiHF9610
Vishay Siliconix
Power MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
• Dynamic dV/dt Rating
- 200
RDS(on) (Ω)
VGS = - 10 V
Qg (Max.) (nC)
11
Qgs (nC)
7.0
Qgd (nC)
4.0
Configuration
• P-Channel
3.0
RoHS*
• Ease of Paralleling
COMPLIANT
• Simple Drive Requirements
• Lead (Pb)-free Available
Single
DESCRIPTION
S
The Power MOSFETs technology is the key to Vishay’s
advanced line of Power MOSFET transistors. The efficient
geometry and unique processing of the Power MOSFETs
design achieve very low on-state resistance combined with
high transconductance and extreme device ruggedness.
TO-220
G
The TO-220 package is universally preferred for all
commercial-industrial applications at power dissipation
levels to approximately 50 W. The low thermal resistance
and low package cost of the TO-220 contribute to its wide
acceptance throughout the industry.
S
G
Available
• Fast Switching
D
D
P-Channel MOSFET
ORDERING INFORMATION
Package
TO-220
IRF9610PbF
SiHF9610-E3
IRF9610
SiHF9610
Lead (Pb)-free
SnPb
ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
LIMIT
Drain-Source Voltage
VDS
- 200
Gate-Source Voltage
VGS
± 20
Continuous Drain Current
Pulsed Drain
VGS at - 10 V
TC = 25
ID
TC = 100
Currenta
IDM
Linear Derating Factor
TC = 25 °C
Maximum Power Dissipation
PD
Inductive Current, Clamp
Operating Junction and Storage Temperature Range
Mounting Torque
V
- 1.8
- 1.0
A
- 7.0
0.16
W/°C
20
W
ILM
- 7.0
A
dV/dt
- 5.0
V/ns
TJ, Tstg
- 55 to + 150
Peak Diode Recovery dV/dtc
Soldering Recommendations (Peak Temperature)
UNIT
for 10 s
6-32 or M3 screw
300d
°C
10
lbf · in
1.1
N·m
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 5).
b. Not applicable.
c. ISD ≤ - 1.8 A, dI/dt ≤ 70 A/µs, VDD ≤ VDS, TJ ≤ 150 °C.
d. 1.6 mm from case.
* Pb containing terminations are not RoHS compliant, exemptions may apply
Document Number: 91080
S-Pending-Rev. A, 20-Jun-08
WORK-IN-PROGRESS
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IRF9610, SiHF9610
Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
Maximum Junction-to-Ambient
RthJA
-
62
Case-to-Sink, Flat, Greased Surface
RthCS
0.50
-
Maximum Junction-to-Case (Drain)
RthJC
-
6.4
UNIT
°C/W
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
VDS
VGS = 0 V, ID = - 250 µA
- 200
-
-
V
ΔVDS/TJ
Reference to 25 °C, ID = - 1 mA
-
- 0.23
-
V/°C
VGS(th)
VDS = VGS, ID = - 250 µA
- 2.0
-
- 4.0
V
Gate-Source Leakage
IGSS
VGS = ± 20 V
-
-
± 100
nA
Zero Gate Voltage Drain Current
IDSS
VDS = - 200 V, VGS = 0 V
-
-
- 100
VDS = - 160 V, VGS = 0 V, TJ = 125 °C
-
-
- 500
Gate-Source Threshold Voltage
Drain-Source On-State Resistance
Forward Transconductance
RDS(on)
gfs
ID = -0.90 Ab
VGS = - 10 V
VDS = - 50 V, ID = - 0.90 Ab
µA
-
-
3.0
Ω
0.90
-
-
S
-
170
-
-
50
-
Dynamic
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Total Gate Charge
Qg
Gate-Source Charge
Qgs
VGS = 0 V,
VDS = - 25 V,
f = 1.0 MHz, see fig. 10
VGS = - 10 V
ID = - 3.5 A, VDS = - 160 V,
see fig. 11 and 18b
-
15
-
-
-
11
-
-
7.0
pF
nC
Gate-Drain Charge
Qgd
-
-
4.0
Turn-On Delay Time
td(on)
-
8.0
-
-
15
-
-
10
-
-
8.0
-
-
4.5
-
-
7.5
-
-
-
- 1.8
-
-
- 7.0
-
-
- 5.8
V
-
240
360
ns
-
1.7
2.6
µC
Rise Time
Turn-Off Delay Time
Fall Time
tr
td(off)
VDD = - 100 V, ID = - 0.90 A,
RG = 50 Ω, RD = 11 Ω, see fig. 17b
tf
Internal Drain Inductance
LD
Internal Source Inductance
LS
Between lead,
6 mm (0.25") from
package and center of
die contact
D
ns
nH
G
S
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulsed Diode Forward Currenta
ISM
Body Diode Voltage
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Forward Turn-On Time
ton
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
S
TJ = 25 °C, IS = - 1.8 A, VGS = 0 Vb
TJ = 25 °C, IF = - 1.8 A, dI/dt = 100 A/µsb
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 5).
b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %.
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Document Number: 91080
S-Pending-Rev. A, 20-Jun-08
IRF9610, SiHF9610
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Fig. 1 - Typical Output Characteristics
Fig. 2 - Typical Transfer Characteristics
Fig. 3 - Typical Saturation Characteristics
Fig. 4 - Maximum Safe Operating Area
Fig. 5 - Maximum Effective Transient Thermal Impedance, Junction-to-Case vs. Pulse Duration
Document Number: 91080
S-Pending-Rev. A, 20-Jun-08
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IRF9610, SiHF9610
Vishay Siliconix
Fig. 6 - Typical Transconductance vs. Drain Current
Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 8 - Breakdown Voltage vs. Temperature
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Fig. 9 - Normalized On-Resistance vs. Temperature
Fig. 10 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 11 - Typical Gate Charge vs. Gate-to-Source Voltage
Document Number: 91080
S-Pending-Rev. A, 20-Jun-08
IRF9610, SiHF9610
Vishay Siliconix
Fig. 12 - Typical On-Resistance vs. Drain Current
Fig. 13 - Maximum Drain Current vs. Case Temperature
Fig. 14 - Power vs. Temperature Derating Curve
L
VDD
Vary tp to obtain
required IL
VGS = - 10 V
tp
VDS
D.U.T.
V DD
+
EC
IL
0.05 Ω
IL
VDD = 0.5 VDS
tp
EC = 0.75 VDS
Fig. 15 - Clamped Inductive Test Circult
Document Number: 91080
S-Pending-Rev. A, 20-Jun-08
VDS
EC
Fig. 16 - Clamped Inductive Waveforms
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IRF9610, SiHF9610
Vishay Siliconix
RD
VDS
QG
15 V
VGS
D.U.T.
RG
QGS
+VDD
QGD
VG
- 10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
Charge
Fig. 17a - Switching Time Test Circuit
Fig. 18a - Basic Gate Charge Waveform
Current regulator
Same type as D.U.T.
td(on)
tr
td(off) tf
VGS
50 kΩ
12 V
0.2 µF
0.3 µF
10 %
-
D.U.T.
90 %
VDS
+ VDS
VGS
- 3 mA
IG
ID
Current sampling resistors
Fig. 17b - Switching Time Waveforms
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Fig. 18b - Gate Charge Test Circuit
Document Number: 91080
S-Pending-Rev. A, 20-Jun-08
IRF9610, SiHF9610
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
D.U.T.
+
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
RG
+
• dV/dt controlled by RG
• ISD controlled by duty factor "D"
• D.U.T. - device under test
+
- VDD
Compliment N-Channel of D.U.T. for driver
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = - 10 V*
D.U.T. ISD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
VDD
Body diode forward drop
Inductor current
Ripple ≤ 5 %
*
ISD
VGS = - 5 V for logic level and - 3 V drive devices
Fig. 19 - For P-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see http://www.vishay.com/ppg?91080.
Document Number: 91080
S-Pending-Rev. A, 20-Jun-08
www.vishay.com
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Vishay
Disclaimer
All product specifications and data are subject to change without notice.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf
(collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein
or in any other disclosure relating to any product.
Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any
information provided herein to the maximum extent permitted by law. The product specifications do not expand or
otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed
therein, which apply to these products.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this
document or by any conduct of Vishay.
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Document Number: 91000
Revision: 18-Jul-08
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